參數(shù)資料
型號： CY7C63723C
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結合低速USB和PS/2外設控制器)
中文描述： 的enCoRe USB的組合低速USB和PS / 2外設控制器（的enCoRe的USB結合低速的USB和的PS / 2外設控制器）
文件頁數(shù)： 19/49頁
文件大?。?/td> 1942K
代理商： CY7C63723C
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 19 of 49
In addition, the Mode Bits are automatically changed by the
SIE in response to many USB transactions. For example, if
the Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK
IN mode as shown in
Table 22-1
, the SIE will change the
endpoint Mode Bit [3:0] to NAK IN/OUT (0001) mode after
issuing an ACK handshake in response to an OUT token.
Firmware needs to update the mode for the SIE to respond
appropriately.
14.3
The CY7C637xxC feature two non-control endpoints, endpoint
1 (EP1) and endpoint 2 (EP2). The EP1 and EP2 Mode
Registers do not have the locking mechanism of the EP0
Mode Register. The EP1 and EP2 Mode Registers use the
format shown in
Figure 14-3
. EP1 uses an 8-byte FIFO at
SRAM locations 0xF0–0xF7, EP2 uses an 8-byte FIFO at
SRAM locations 0xE8–0xEF as shown in Section 8.2.
USB Non-control Endpoints
Bit 7: STALL
1 = The SIE will stall an OUT packet if the Mode Bits are set
to ACK-OUT, and the SIE will stall an IN packet if the mode
bits are set to ACK-IN. See Section 22.0 for the available
modes.
0 = This bit must be set to LOW for all other modes.
Bit [6:5]:
Reserved. Must be written to zero during register
writes.
Bit 4: ACKed Transaction
The ACKed transaction bit is set whenever the SIE engag-
es in a transaction to the register's endpoint that completes
with an ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode Bit [3:0]
The EP1 and EP2 Mode Bits operate in the same manner
as the EP0 Mode Bits (see Section 14.2).
14.4
There are three Endpoint Counter registers, with identical
formats for both control and non-control endpoints. These
registers contain byte count information for USB transactions,
as well as bits for data packet status. The format of these
registers is shown in
Figure 14-4
.
USB Endpoint Counter Registers
Bit 7: Data Toggle
This bit selects the DATA packet's toggle state. For IN
transactions, firmware must set this bit to the select the
transmitted Data Toggle. For OUT or SETUP transactions,
the hardware sets this bit to the state of the received Data
Toggle bit.
1 = DATA1
0 = DATA0
Bit 6: Data Valid
This bit is used for OUT and SETUP tokens only. This bit is
cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred.
This bit does not update for some endpoint mode settings.
Refer to
Table 22-3
for more details.
1 = Data is valid.
0 = Data is invalid. If enabled, the endpoint interrupt will
occur even if invalid data is received.
Bit [5:4]:
Reserved
Bit [3:0]: Byte Count Bit [3:0]
Byte Count Bits indicate the number of data bytes in a
transaction: For IN transactions, firmware loads the count
with the number of bytes to be transmitted to the host from
the endpoint FIFO. Valid values are 0 to 8 inclusive. For
OUT or SETUP transactions, the count is updated by hard-
ware to the number of data bytes received, plus 2 for the
CRC bytes. Valid values are 2 to 10 inclusive.
For Endpoint 0 Count Register, whenever the count up-
dates from a SETUP or OUT transaction, the count register
locks and cannot be written by the CPU. Reading the reg-
ister unlocks it. This prevents firmware from overwriting a
status update on incoming SETUP or OUT transactions be-
fore firmware has a chance to read the data.
Bit #
7
6
5
4
3
2
1
0
Bit
Name
STALL Reserved
ACKed
Transaction
Mode Bit
Read/
Write
R/W
-
-
R/C
R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Ad-
dresses 0x14 and 0x16)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Data
Toggle
Data
Valid
Reserved
Byte Count
Read/Writ
e
R/W
R/W
-
-
R/
W
R/
W
R/
W
R/
W
Reset
0
0
0
0
0
0
0
0
Figure 14-4. Endpoint 0,1,2 Counter Registers
(Addresses 0x11, 0x13 and 0x15)
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相關代理商/技術參數(shù)
參數(shù)描述
CY7C63723C-PXC 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63723C-SXC 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63723C-SXCT 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63723-PC 功能描述:IC MCU 8K LS USB/PS-2 18-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應用:網(wǎng)絡處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應商設備封裝:PG-LQFP-208 其它名稱:SP000314382
CY7C63723-PXC 功能描述:IC MCU 8K USB/PS2 LS 18DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應用:網(wǎng)絡處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應商設備封裝:PG-LQFP-208 其它名稱:SP000314382
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