參數(shù)資料
型號: CY7C63723C
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
中文描述: 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器(的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器)
文件頁數(shù): 24/49頁
文件大?。?/td> 1942K
代理商: CY7C63723C
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 24 of 49
18.0
12-bit Free-running Timer
The 12-bit timer operates with a 1-
μ
s tick, provides two inter-
rupts (128-
μ
s and 1.024-ms) and allows the firmware to
directly time events that are up to 4 ms in duration. The lower
eight bits of the timer can be read directly by the firmware.
Reading the lower eight bits latches the upper four bits into a
temporary register. When the firmware reads the upper four
bits of the timer, it is actually reading the count stored in the
temporary register. The effect of this is to ensure a stable 12-bit
timer value can be read, even when the two reads are
separated in time.
Bit [7:0]: Timer lower eight bits
Bit [7:4]:
Reserved
Bit [3:0]: Timer upper four bits
Bit #
7
6
5
4
3
2
1
0
Bit Name
Timer [7:0]
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 18-1. Timer LSB Register (Address 0x24)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
Timer [11:8]
Read/Write
-
-
-
-
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 18-2. Timer MSB Register (Address 0x25)
Figure 18-3. Timer Block Diagram
10
9
7
8
5
6
4
3
2
1 MHz clock
1.024-ms interrupt
128-
μ
s interrupt
To Timer Registers
8
1
0
11
L1
L0
L2
L3
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
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