參數(shù)資料
型號: CY7C63723C
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
中文描述: 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器(的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器)
文件頁數(shù): 26/49頁
文件大?。?/td> 1942K
代理商: CY7C63723C
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 26 of 49
Bit [7:4]:
Reserved.
Bit [3:0]: Capture A/B, Falling/Rising Event
These bits record the occurrence of any rising or falling
edges on the capture GPIO pins. Bits in this register are
cleared by reading the corresponding data register.
1 = A rising or falling event that matches the pin’s rising/fall-
ing condition has occurred.
0 = No event that matches the pin’s rising or falling edge
condition.
Because both Capture A events (rising and falling) share
an interrupt, user’s firmware needs to check the status of
both Capture A Falling and Rising Event bits to determine
what caused the interrupt. This is also true for Capture B
events.
Bit 7: First Edge Hold
1 = The time of the first occurrence of an edge is held in the
Capture Timer Data Register until the data is read. Subse-
quent edges are ignored until the Capture Timer Data Reg-
ister is read.
0 = The time of the most recent edge is held in the Capture
Timer Data Register. That is, if multiple edges have oc-
curred before reading the capture timer, the time for the last
one will be read (default state).
The First Edge Hold function applies globally to all four cap-
ture timers.
Bit [6:4]: Prescale Bit [2:0]
Three prescaler bits allow the capture timer clock rate to be
selected among 5 choices, as shown in
Table 19-1
below.
Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable
Each of the four Capture Timer registers can be individually
enabled to provide interrupts.
Both Capture A events share a common interrupt request,
as do the two Capture B events. In addition to the event
enables, the main Capture Interrupt Enables bit in the Glo-
bal Interrupt Enable register (Section 21.0) must be set to
activate a capture interrupt.
1 = Enable interrupt
0 = Disable interrupt
Table 19-1. Capture Timer Prescalar Settings (Step size
and range for F
CLK
= 6 MHz)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture A Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-3. Capture Timer A-Falling, Data Register
(Address 0x41)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Rising Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-4. Capture Timer B-Rising, Data Register
(Address 0x42)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-5. Capture Timer B-Falling, Data Register
(Address 0x43)
Bit #
7
6
5
4
3
2
1
0
Bit
Name
Reserved
Capture
B
Falling
Event
Capture
B
Rising
Event
Capture
A
Falling
Event
Capture
A
Rising
Event
Read/
Write
-
-
-
-
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-6. Capture Timer Status Register (Address 0x45)
Bit #
7
6
5
4
3
2
1
0
Bit
Name
First
Edge
Hold
Prescale Bit
[2:0]
Capture
B
Falling
Int
Enable
Capture
B
Rising
Int
Enable
Capture
A
Falling
Int
Enable
Capture
A
Rising
Int
Enable
Read/
Write
R/W R/W R/W R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 19-7. Capture Timer Configuration Register
(Address 0x44)
Prescale
2:0
Captured Bits
LSB
Step
Size
1
μ
s
2
μ
s
4
μ
s
8
μ
s
16
μ
s
Range
256
μ
s
512
μ
s
000
Bits 7:0 of free-running timer
001
Bits 8:1 of free-running timer
010
Bits 9:2 of free-running timer
1.024 ms
011
Bits 10:3 of free-running timer
2.048 ms
100
Bits 11:4 of free-running timer
4.096 ms
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