參數(shù)資料
型號: CY7C63723C
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
中文描述: 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器(的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器)
文件頁數(shù): 31/49頁
文件大?。?/td> 1942K
代理商: CY7C63723C
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 31 of 49
Bit [7:0]: P0 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
Bit [7:0]: P1 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers.
Figure 21-6
and
Figure 21-7
control the interrupt
polarity of each GPIO pin.
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Figure 21-3. Interrupt Controller Logic Block Diagram
CLR
Global
Interrupt
Enable
Bit
Interrupt
Acknowledge
IRQout
USB-PS/2 Clear
Interrupt
Vector
Interrupt
Priority
Encoder
Enable [0]
(Reg 0x20)
D
Q
1
CLR
USB-PS/2 IRQ
128-
μ
s CLR
128-
μ
s IRQ
1-ms CLR
1-ms IRQ
EP0 CLR
EP0 IRQ
Wake-up IRQ
Enable [7]
(Reg 0x20)
CLK
CLR
D
Q
CLK
1
Wake-up CLR
Int
Wake-up
Int
USB-
PS/2
EP1 IRQ
EP2 CLR
EP1 CLR
IRQ Pending
(Bit 7, Reg 0xFF)
IRQ
Controlled by DI, EI, and
RETI Instructions
To CPU
CPU
GPIO IRQ
GPIO CLR
EP2 IRQ
SPI CLR
Capture A IRQ
Capture A CLR
Capture B IRQ
Capture B CLR
CLR
D
Enable [2]
(Reg 0x21)
Q
1
CLK
Int
EP2
Int Enable
Sense
(Bit 2, Reg 0xFF)
SPI IRQ
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0 Interrupt Enable
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-4. Port 0 Interrupt Enable Register (Address
0x04)
Bit #
7
6
5
4
3
2
1
0
Bit Name
P1 Interrupt Enable
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-5. Port 1 Interrupt Enable Register
(Address 0x05)
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0 Interrupt Polarity
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-6. Port 0 Interrupt Polarity Register
(Address 0x06)
Bit #
7
6
5
4
3
2
1
0
Bit Name
P1 Interrupt Polarity
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-7. Port 1 Interrupt Polarity Register
(Address 0x07)
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CY7C63723C-PXC 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
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