參數(shù)資料
型號: CY7C63743-PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDIP24
封裝: 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù): 4/58頁
文件大?。?/td> 1236K
代理商: CY7C63743-PC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 4 of 58
Figure 17-4. SPI Data Timing ..............................................................................................................31
Figure 18-1. Timer LSB Register (Address 0x24) ................................................................................31
Figure 18-2. Timer MSB Register (Address 0x25) ...............................................................................32
Figure 18-3. Timer Block Diagram .......................................................................................................32
Figure 19-1. Capture Timers Block Diagram .......................................................................................33
Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) .................................................33
Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) .................................................34
Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) .................................................34
Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) .................................................34
Figure 19-6. Capture Timer Status Register (Address 0x45) ..............................................................34
Figure 19-7. Capture Timer Configuration Register (Address 0x44) ...................................................34
Figure 20-1. Processor Status and Control Register (Address 0xFF) .................................................35
Figure 21-1. Global Interrupt Enable Register (Address 0x20) ............................................................38
Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) ........................................................39
Figure 21-3. Interrupt Controller Logic Block Diagram ........................................................................40
Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) ............................................................40
Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) ............................................................40
Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) ............................................................41
Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) ............................................................41
Figure 21-8. GPIO Interrupt Diagram ..................................................................................................41
Figure 26-1. Clock Timing ....................................................................................................................51
Figure 26-2. USB Data Signal Timing ..................................................................................................51
Figure 26-3. Receiver Jitter Tolerance ................................................................................................52
Figure 26-4. Differential to EOP Transition Skew and EOP Width ......................................................52
Figure 26-5. Differential Data Jitter ......................................................................................................52
Figure 26-7. SPI Slave Timing, CPHA = 0 ...........................................................................................53
Figure 26-6. SPI Master Timing, CPHA = 0 .........................................................................................53
Figure 26-8. SPI Master Timing, CPHA = 1 .........................................................................................54
Figure 26-9. SPI Slave Timing, CPHA = 1 ...........................................................................................54
LIST OF TABLES
Table 8-1. I/O Register Summary ........................................................................................................13
Table 11-1. Wake-up Timer Adjust Settings ........................................................................................18
Table 12-1. Ports 0 and 1 Output Control Truth Table ........................................................................21
Table 13-1. Control Modes to Force D+/D– Outputs ...........................................................................24
Table 17-1. SPI Pin Assignments ........................................................................................................31
Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ...................35
Table 21-1. Interrupt Vector Assignments ...........................................................................................37
Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints ............................42
Table 22-2. Decode table for
Table 22-3
: “Details of Modes for Differing Traffic Conditions” .............44
Table 22-3. Details of Modes for Differing Traffic Conditions ..............................................................45
Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) ............57
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