參數(shù)資料
型號(hào): CY7C63743
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 的enCoRe USB的組合低速USB
文件頁(yè)數(shù): 22/58頁(yè)
文件大?。?/td> 1236K
代理商: CY7C63743
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 22 of 58
Bit [3:2]:
Reserved
Bit 1: P2.1 (Internal Clock Mode Only)
In the Internal Clock mode, the XTALIN pin can serve as a general purpose input, and its state can be read at Port 2, Bit 1
(P2.1). See Section 9.1 for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit 0: P2.0/VREG Pin State
In PS/2 mode, the VREG
pin can be used as an input and its state can be read at port P2.0. Section 15.0 for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
13.0
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB host. The SIE simplifies the interface between the microcon-
troller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller:
Translate the encoded received data and format the data to be transmitted on the bus.
CRC checking and generation. Flag the microcontroller if errors exist during transmission.
Address checking. Ignore the transactions not addressed to the device.
Send appropriate ACK/NAK/STALL handshakes.
Token type identification (SETUP, IN, or OUT). Set the appropriate token bit once a valid token is received.
Place valid received data in the appropriate endpoint FIFOs.
Send and update the data toggle bit (Data1/0).
Bit stuffing/unstuffing.
Firmware is required to handle the rest of the USB interface with the following tasks:
Coordinate enumeration by decoding USB device requests.
Fill and empty the FIFOs.
Suspend/Resume coordination.
Verify and select Data toggle values.
13.1
A typical USB enumeration sequence is shown below. In this description, ‘Firmware’ refers to embedded firmware in the
CY7C637xx controller.
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB
bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB
address to the device.
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
10.Once the device receives a Set Configuration request, its functions may now be used.
11.Firmware should take appropriate action for Endpoint 1 and/or 2 transactions, which may occur from this point.
USB Enumeration
13.2
USB status and control is regulated by the USB Status and Control Register as shown in
Figure 13-1
.
USB Port Status and Control
相關(guān)PDF資料
PDF描述
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63310 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
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