參數(shù)資料
型號(hào)： CY7C63743
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述： 的enCoRe USB的組合低速USB
文件頁數(shù)： 25/58頁
文件大?。?/td> 1236K
代理商： CY7C63743
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 25 of 58
The SIE provides a locking feature to prevent firmware from overwriting bits in the USB Endpoint 0 Mode Register. Writes to the
register have no effect from the point that Bit[6:0] of the register are updated (by the SIE) until the firmware reads this register.
The CPU can unlock this register by reading it.
Because of these hardware-locking features, firmware should perform an read after a write to the USB Endpoint 0 Mode Register
and USB Endpoint 0 Count Register (
Figure 14-4
) to verify that the contents have changed as desired, and that the SIE has not
updated these values.
Bit [7:4] of this register are cleared by any non-locked write to this register, regardless of the value written.
Bit 7: SETUP Received
1 = A valid SETUP packet has been received. This bit is forced HIGH from the start of the data packet phase of the SETUP
transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval.
While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
0 = No SETUP received. This bit is cleared by any non-locked writes to the register.
Bit 6: IN Received
1 = A valid IN packet has been received. This bit is updated to ‘1’ after the last received packet in an IN transaction. This bit
is cleared by any non-locked writes to the register.
0 = No IN received. This bit is cleared by any non-locked writes to the register.
Bit 5: OUT Received
1 = A valid OUT packet has been received. This bit is updated to ‘1’ after the last received packet in an OUT transaction. This
bit is cleared by any non-locked writes to the register.
0 = No OUT received. This bit is cleared by any non-locked writes to the register.
Bit 4: ACKed Transaction
The ACKed Transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an
ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode Bit[3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. For example, if the
endpoint Mode Bits [3:0] are set to 0001 which is NAK IN/OUT mode as shown in
Table 22-1
, the SIE will send NAK hand-
shakes in response to any IN or OUT token sent to this endpoint. In this NAK IN/OUT mode, the SIE will send an ACK
handshake when the host sends a SETUP token to this endpoint. The mode encoding is shown in
Table 22-1
. Additional
information on the mode bits can be found in
Table 22-2
and
Table 22-3
. These modes give the firmware total control on how
to respond to different tokens sent to the endpoints from the host.
In addition, the Mode Bits are automatically changed by the SIE in response to many USB transactions. For example, if the
Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK IN mode as shown in
Table 22-1
, the SIE will change the endpoint
Mode Bit [3:0] to NAK IN/OUT (0001) mode after issuing an ACK handshake in response to an OUT token. Firmware needs
to update the mode for the SIE to respond appropriately.
14.3
The CY7C637xx feature two non-control endpoints, endpoint 1 (EP1) and endpoint 2 (EP2). The EP1 and EP2 Mode Registers
do not have the locking mechanism of the EP0 Mode Register. The EP1 and EP2 Mode Registers use the format shown in
Figure 14-3
. EP1 uses an 8-byte FIFO at SRAM locations 0xF0–0xF7, EP2 uses an 8-byte FIFO at SRAM locations 0xE8–0xEF
as shown in Section 8.2.
USB Non-control Endpoints
Bit #
7
6
5
4
3
2
1
0
Bit Name
SETUP
Received
IN
Received
OUT
Received
ACKed
Transaction
Mode Bit
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 14-2. Endpoint 0 Mode Register (Address 0x12)
相關(guān)PDF資料
PDF描述
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63310 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C63743C-PXC 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743C-QXC 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743C-SXC 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743C-SXCT 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743-PC 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382
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