參數(shù)資料
型號(hào)： CY7C63743
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述： 的enCoRe USB的組合低速USB
文件頁(yè)數(shù)： 31/58頁(yè)
文件大?。?/td> 1236K
代理商： CY7C63743
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 31 of 58
17.5
For SPI, an interrupt request is generated after a byte is received or transmitted. See Section
21.3 for details on the SPI interrupt.
SPI Interrupt
17.6
The GPIO pins used for SPI outputs (P0.5–P0.7) contain a bypass mode, as shown in the GPIO block diagram (
Figure 12-1
).
Whenever the SPI block is inactive (Mode[5:4] = 00), the bypass value is 1, which enables normal GPIO operation. When SPI
master or slave modes are activated, the appropriate bypass signals are driven by the hardware for outputs, and are held at 1
for inputs.
Note that the corresponding data bits in the Port 0 Data Register must be set to 1 for each pin being used for
an SPI output.
In addition, the GPIO modes are not affected by operation of the SPI block, so each pin must be programmed by
firmware to the desired drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI bypass value in
Figure 12-1
is always 1, for normal GPIO operation.
SPI Modes for GPIO Pins
18.0
12-bit Free-running Timer
The 12-bit timer operates with a 1-
μ
s tick, provides two interrupts (128-
μ
s and 1.024-ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits
latches the upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is actually reading the
count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two
reads are separated in time.
Table 17-1. SPI Pin Assignments
SPI Function
GPIO Pin
Comment
Slave Select (SS)
P0.4
For Master Mode, Firmware sets SS, may use any GPIO pin.
For Slave Mode, SS is an active LOW input.
Master Out, Slave In (MOSI)
P0.5
Data output for master, data input for slave.
Master In, Slave Out (MISO)
P0.6
Data input for master, data output for slave.
SCK
P0.7
SPI Clock: Output for master, input for slave.
Bit #
7
6
5
4
3
2
1
0
Bit Name
Timer [7:0]
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 18-1. Timer LSB Register (Address 0x24)
MSB
LSB
x
SS
SCK (CPOL = 1)
SCK (CPOL = 0)
MOSI/MISO
MSB
LSB
x
MOSI/MISO
Data Capture Strobe
Data Capture Strobe
Interrupt Issued
Interrupt Issued
CPHA = 1:
CPHA = 0:
Figure 17-4. SPI Data Timing
相關(guān)PDF資料
PDF描述
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
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