參數(shù)資料
型號: CY7C63743
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 的enCoRe USB的組合低速USB
文件頁數(shù): 44/58頁
文件大?。?/td> 1236K
代理商: CY7C63743
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 44 of 58
The response of the SIE can be summarized as follows:
1. The SIE will only respond to valid transactions, and will ignore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs
during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.
3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa versa.
5. The IN and OUT PID status is updated at the end of a transaction.
6. The SETUP PID status is updated at the beginning of the Data packet phase.
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of these registers, and only if that
read happens after the transaction completes. This represents about a 1-
μ
s window in which the CPU is locked from register
writes to these USB registers. Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to
unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made during the previous transaction.
Table 22-2. Decode table for
Table 22-3
: “Details of Modes for Differing Traffic Conditions”
Endpoint Mode
Encoding
Properties of incoming
packet
Changes to the internal register made by the SIE as a result of
the incoming token
Interrupt
End Point
Mode
3
2
1
0
Token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
3
2
1
0
Response
Int
Bit[3:0],
Figure 14-4
SIE’s Response
Data Valid (Bit 6,
Figure 14-4
)
Endpoint Mode changed
by the SIE.
Data 0/1 (Bit 7,
Figure 14-4
)
Received Token
(SETUP, IN,OUT)
The validity of the received data
Acknowledge transaction completed
(Bit4,
Figure 14-2
/3)
The quality status of the DMA buffer
PID Status Bits
(Bit[7:5],
Figure 14-2
)
The number of received bytes
Legend:
UC: unchanged
TX: transmit
TX0: transmit 0-length packet
x: don’t care
RX: receive
available for Control endpoint only
相關(guān)PDF資料
PDF描述
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63310 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
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