參數(shù)資料
型號: CY7C63743
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 的enCoRe USB的組合低速USB
文件頁數(shù): 47/58頁
文件大?。?/td> 1236K
代理商: CY7C63743
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 47 of 58
23.0
Register Summary
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write/
Both/
Default/
Reset
G
0x00
Port 0 Data
P0
BBBBBBBB
00000000
0x01
Port 1 Data
P1
BBBBBBBB
00000000
0x02
Port 2 Data
Reserved
D+(SCLK)
State
D- (SDATA)
State
Reserved
P2.1 (Int Clk
Mode Only
VREG Pin
State
--
RR
--
RR
00000000
0x0A
GPIO Port 0 Mode 0
P0[7:0] Mode0
WWWWWWWW
00000000
0x0B
GPIO Port 0 Mode 1
P0[7:0] Mode1
WWWWWWWW
00000000
0x0C
GPIO Port 1 Mode 0
P1[7:0] Mode0
WWWWWWWW
00000000
0x0D
GPIO Port 1 Mode 1
P1[7:0] Mode1
WWWWWWWW
00000000
0x04
Port 0 Interrupt Enable
P0[7:0] Interrupt Enable
WWWWWWWW
00000000
0x05
Port 1 Interrupt Enable
P1[7:0] Interrupt Enable
WWWWWWWW
00000000
0x06
Port 0 Interrupt Polarity
P0[7:0] Interrupt Polarity
WWWWWWWW
00000000
0x07
Port 1 Interrupt Polarity
P1[7:0] Interrupt Polarity
WWWWWWWW
00000000
C
C
0xF8
Clock Configuration
Ext. Clock
Resume
Delay
Wake-up Timer Adjust Bit [2:0]
Low-voltage
Reset
Disable
Precision
USB
Clocking
Enable
Internal
Clock
Output
Disable
External
Oscillator
Enable
BBBBBBBB
00000000
E
C
0x10
USB Device Address
Device
Address
Enable
Device Address
BBBBBBBB
00000000
0x12
EP0 Mode
SETUP
Received
IN
Received
OUT
Received
ACKed
Transaction
Mode Bit
BBBBBBBB
00000000
0x14,
0x16
EP1, EP2 Mode Register
STALL
Reserved
ACKed
Transaction
Mode Bit
B
--
BBBBB
00000000
0x11,
0x13, and
0x15
EP0,1, and 2 Counter
Data 0/1
Toggle
Data Valid
Reserved
Byte Count
BB
--
BBBB
00000000
U
S
0x1F
USB Status and Control
PS/2 Pull-up
Enable
VREG
Enable
USB
Reset-PS/2
Activity
Interrupt
Mode
Reserved
USB Bus
Activity
D+/D- Forcing Bit
BBB
-
BBBB
00000000
I
0x20
Global Interrupt Enable
Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Timer B Intr.
Enable
Capture
Timer A Intr.
Enable
SPI
Interrupt
Enable
1.024 ms
Interrupt
Enable
128
μ
s
Interrupt
Enable
USB Bus
Reset-PS/2
Activity Intr.
Enable
BBBBBBBB
00000000
0x21
Endpoint Interrupt Enable
Reserved
EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
-----
BBB
00000000
T
0x24
Timer LSB
Timer Bit [7:0]
RRRRRRRR
00000000
0x25
Timer (MSB)
Reserved
Timer Bit [11:8]
----
RRRR
00000000
S
0x60
SPI Data
Data I/O
BBBBBBBB
00000000
0x61
SPI Control
TCMP
TBF
Comm Mode [1:0]
CPOL
CPHA
SCK Select
BBBBBBBB
00000000
C
0x40
Capture Timer A-Rising,
Data Register
Capture A Rising Data
RRRRRRRR
00000000
0x41
Capture Timer A-Falling,
Data Register
Capture A Falling Data
RRRRRRRR
00000000
0x42
Capture Timer B-Rising,
Data Register
Capture B Rising Data
RRRRRRRR
00000000
0x43
Capture Timer B-Falling,
Data Register
Capture B Falling Data
RRRRRRRR
00000000
0x44
Capture Timer
Configuration
First Edge
Hold
Prescale Bit [2:0]
Capture B
Falling Intr
Enable
Capture B
Rising Intr
Enable
Capture A
Falling Intr
Enable
Capture A
Rising Intr
Enable
BBBBBBBB
00000000
0x45
Capture Timer Status
Reserved
Capture B
Falling
Event
Capture B
Rising Event
Capture A
Falling
Event
Capture A
Rising Event
----
BBBB
00000000
P
S
0xFF
Process Status & Control
IRQ
Pending
Watch Dog
Reset
Bus
Interrupt
Event
LVR/BOR
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
RBBBBR
-
B
See
Section
20.0
相關PDF資料
PDF描述
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結合低速USB和PS/2外設控制器)
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