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參數(shù)資料
| 型號(hào)： | CY7C63743C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| 中文描述： | 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器（的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器） |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 1942K |
| 代理商： | CY7C63743C |
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CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 29 of 49
21.3
The following sections provide details on the different types of
interrupt sources.
Interrupt Sources
Bit 7: Wake-up Interrupt Enable
The internal wake-up timer is normally used to wake the
part from suspend mode, but it can also provide an interrupt
when the part is awake. The wake-up timer is cleared
whenever the Wake-up Interrupt Enable bit is written to a 0,
and runs whenever that bit is written to a 1. When the inter-
rupt is enabled, the wake-up timer provides periodic inter-
rupts at multiples of period, as described in Section 11.2.
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Bit 6: GPIO Interrupt Enable
Each GPIO pin can serve as an interrupt input. During a
reset, GPIO interrupts are disabled by clearing all GPIO
interrupt enable registers. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding
input pin. These registers are shown in
Figure 21-4
for Port
0 and
Figure 21-5
for Port 1. In addition to enabling the
desired individual pins for interrupt, the main GPIO interrupt
must be enabled, as explained in Section 21.0.
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers. Setting a Polarity bit to ‘0’ allows an interrupt on
a falling GPIO edge, while setting a Polarity bit to ‘1’ allows
an interrupt on a rising GPIO edge. The Polarity Registers
reset to 0 and are shown in
Figure 21-6
for Port 0 and
Figure 21-7
for Port 1.
All of the GPIO pins share a single interrupt vector, which
means the firmware will need to read the GPIO ports with
enabled interrupts to determine which pin or pins caused
an interrupt.The GPIO interrupt structure is illustrated in
Figure 21-8
.
Note that if one port pin triggered an interrupt, no other port
pins can cause a GPIO interrupt until that port pin has re-
turned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The CY7C637xxC does
not assign interrupt priority to different port pins and the
Port Interrupt Enable Registers are not affected by the in-
terrupt acknowledge process.
1 = Enable
0 = Disable
Bit [5:4]: Capture Timer A and B Interrupts
There are two capture timer interrupts, one for each
associated pin. Each of these interrupts occurs on an enabled
edge of the selected GPIO pin(s). For each pin, rising and/or
falling edge capture interrupts can be in selected. Refer to
Section 19.0. These interrupts are independent of the GPIO
interrupt, described in the next section.
1 = Enable
0 = Disable
Bit 3: SPI Interrupt Enable
The SPI interrupt occurs at the end of each SPI byte trans-
action, at the final clock edge, as shown in
Figure 17-4
. After
the interrupt, the received data byte can be read from the SPI
Data Register, and the TCMP control bit will be high
1 = Enable
0 = Disable
Bit 2: 1.024-ms Interrupt Enable
The 1.024-ms interrupts are periodic timer interrupts from
the free-running timer (based on the 6-MHz clock). The
user should disable this interrupt before going into the sus-
pend mode to avoid possible conflicts between servicing
the timer interrupts (128-
μ
s interrupt and 1.024-ms inter-
rupt) first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 1.024 ms.
0 = Disable.
Bit 1: 128-
μ
s Interrupt Enable
The 128-
μ
s interrupt is another source of timer interrupt
from the free-running timer. The user should disable both
timer interrupts (128-
μ
s and 1.024-ms) before going into
the suspend mode to avoid possible conflicts between ser-
vicing the timer interrupts first or the suspend request first
when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 128
μ
s.
0 = Disable.
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
The function of this interrupt is selectable between detec-
tion of either a USB bus reset condition, or PS/2 activity.
The selection is made with the USB-PS/2 Interrupt Mode
bit in the USB Status and Control Register (
Figure 13-1
). In
either case, the interrupt will occur if the selected condition
exists for 256
μ
s, and may occur as early as 128
μ
s.
Bit #
7
6
5
4
3
2
1
0
Bit Name
Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Timer B
Intr. Enable
Capture
Timer A
Intr. Enable
SPI
Interrupt
Enable
1.024-ms
Interrupt
Enable
128-
μ
s
Interrupt
Enable
USB Bus
Reset /
PS/2 Activity
Intr. Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 21-1. Global Interrupt Enable Register (Address 0x20)
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| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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