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CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 38 of 49
24.0
Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................–65°C to +150°C
Ambient Temperature with Power Applied...............................................................................................................–0°C to +70°C
Supply Voltage on V
CC
Relative to V
SS
..................................................................................................................–0.5V to +7.0V
DC Input Voltage........................................................................................................................................... –0.5V to +V
CC
+0.5V
DC Voltage Applied to Outputs in High Z State............................................................................................ –0.5V to + V
CC
+0.5V
Maximum Total Sink Output Current into Port 0 and 1 and Pins.......................................................................................... 70 mA
Maximum Total Source Output Current into Port 0 and 1 and Pins..................................................................................... 30 mA
Maximum On-chip Power Dissipation on any GPIO Pin......................................................................................................50 mW
Power Dissipation..............................................................................................................................................................300 mW
Static Discharge Voltage .................................................................................................................................................. > 2000V
Latch-up Current ........................................................................................................................................................... > 200 mA
25.0
DC Characteristics
FOSC = 6 MHz; Operating Temperature = 0 to 70°C
Parameter
General
Conditions
Min.
Max.
Unit
V
CC1
V
CC2
I
CC1
Operating Voltage
Operating Voltage
V
CC
Operating Supply Current – Internal
Oscillator Mode
Typical I
CC1
= 16 mA
[5]
V
CC
Operating Supply Current – External
Oscillator Mode
Typical I
CC2
= 13 mA
[5]
Standby Current – No Wake-up Osc
Standby Current – With Wake-up Osc
Programming Voltage (disabled)
Resonator Start-up Interval
Input Leakage Current
Max I
SS
GPIO Sink Current
Max I
CC
GPIO Source Current
Note 4
Note 4
V
CC
= 5.5V, no GPIO loading
V
LVR
4.35
5.5
5.25
20
V
V
V
CC
= 5.0V. T = Room Temperature
V
CC
= 5.5V, no GPIO loading
mA
I
CC2
V
CC
= 5.0V. T = Room Temperature
Oscillator off, D– > 2.7V
Oscillator off, D– > 2.7V
17
mA
I
SB1
I
SB2
V
PP
T
RSNTR
I
IL
I
SNK
I
SRC
25
75
0.4
256
1
70
30
μ
A
μ
A
V
μ
s
μ
A
mA
mA
–0.4
V
CC
= 5.0V, ceramic resonator
Any I/O pin
Cumulative across all ports
[6]
Cumulative across all ports
[6]
Low-Voltage and Power-on Reset
Low-Voltage Reset Trip Voltage
V
CC
Power-on Slew Time
V
LVR
t
VCCS
V
CC
below V
LVR
for >100 ns
[7]
linear ramp: 0 to 4V
[8]
3.5
4.0
100
V
ms
USB Interface
V
REG
C
REG
V
OHU
Notes:
4.
5.
6.
7.
8.
9.
VREG Regulator Output Voltage
Capacitance on VREG Pin
Static Output High, driven
Load = R
PU
+R
PD[9, 10]
External cap not required
R
PD
to Gnd
[4]
3.0
3.6
300
3.6
V
pF
V
2.8
Full functionality is guaranteed in V
range, except USB transmitter specifications and GPIO output currents are guaranteed for V
CC2
range.
Bench measurements taken under nominal operating conditions. Spec cannot be guaranteed at final test.
Total current cumulative across all Port pins, limited to minimize Power and Ground-Drop noise effects.
LVR is automatically disabled during suspend mode.
LVR will re-occur whenever V
drops below V
. In suspend or with LVR disabled, BOR occurs whenever V
drops below approximately 2.5V.
V
specified for regulator enabled, idle conditions (i.e., no USB traffic), with load resistors listed. During USB transmits from the internal SIE, the VREG
output is not regulated, and should not be used as a general source of regulated voltage in that case. During receive of USB data, the VREG output drops
when D– is LOW due to internal series resistance of approximately 200
at the VREG pin.
10. In suspend mode, V
REG
is only valid if R
PU
is connected from D– to VREG pin, and R
PD
is connected from D– to ground.