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參數(shù)資料
| 型號： | CY7C63801 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| 中文描述： | enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器） |
| 文件頁數(shù)： | 54/74頁 |
| 文件大?。?/td> | 1441K |
| 代理商： | CY7C63801 |
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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 54 of 74
21.3
Because both firmware and the SIE are allowed to write to the
Endpoint 0 Mode and Count Registers the SIE provides an
interlocking mechanism to prevent accidental overwriting of
data.
Endpoint 0 Mode
When the SIE writes to these registers they are locked and the
processor cannot write to them until after it has read them.
Writing to this register clears the upper four bits regardless of
the value written.
Table 21-3. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Setup Received
IN Received
R/C
[4]
OUT Received
R/C
[4]
ACK’d Trans
R/C
[4]
Mode[3:0]
Read/Write
R/C[4]
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit 7:
SETUP Received
This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet phase of
the SETUP transactions until the end of the data phase of a control write transfer and cannot be cleared during this interval.
While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
This bit is cleared by any non-locked writes to the register.
0 = No SETUP received
1 = SETUP received
Bit 6:
IN Received
This bit when set indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowledges an IN data
packet.When clear, it indicates either no IN has been received or that the host didn’t acknowledge the IN data by sending ACK
handshake.
This bit is cleared by any non-locked writes to the register.
0 = No IN received
1 = IN received
Bit 5:
OUT Received
This bit when set indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last received
packet in an OUT transaction. When clear, it indicates no OUT received.
This bit is cleared by any non-locked writes to the register.
0 = No OUT received
1 = OUT received
Bit 4:
ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with a ACK
packet.
This bit is cleared by any non-locked writes to the register
1 = The transaction completes with an ACK
0 = The transaction does not complete with an ACK
Bit [3:0]:
Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls
how the USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to
the endpoint.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63801-PXC | 功能描述:USB 接口集成電路 4K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63801-SXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 4K/256 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63801-SXCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C638034-LQXC | 功能描述:IC USB CONTROLLER RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| CY7C638034-SXC | 功能描述:IC USB CONTROLLERS RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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