參數(shù)資料
型號(hào)： CY7C63801
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁(yè)數(shù)： 73/74頁(yè)
文件大?。?/td> 1441K
代理商： CY7C63801
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 73 of 74
Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
30.0
Document History Page
Document Title: CY7C63310/CY7C638xx enCoRe
II Low-Speed USB Peripheral Controller
Document Number: 38-08035
Orig. of
Change
**
131323
12/11/03
XGR
New data sheet
*A
221881
See ECN
KKU
Added Register descriptions and package information, changed from advance
information to preliminary
*B
271232
See ECN
BON
Reformatted
Updated with the latest information
*C
299179
See ECN
BON
Corrected 24-PDIP pinout typo in
Table 5.1
Added
Table 10-1
Updated
Table 9-5
,
Table 10-3
,
Table 13-1
,
Table 17-2
,
Table 17-4
,
Table 17-6
.
and
Table 15-2
. Added various updates to the GPIO Section (
Section 14.0
)
Corrected
Table 15-3
. Corrected
Figure 27-7
and
Figure 27-8
. Added the 16-pin
PDIP package diagram (
Section 29.0
)
*D
322053
See ECN
TVR
Introduction section: Last para removed Low-voltage reset. There is no LVR
there is only LVD (Low voltage detect). explained more about LVD and POR
Changed capture pins from P0.0,P0.1 to P0.5,P0.6
Table 6-1: Changed table heading (Removed Mnemonics and made as Register
names). Table 9-5: Included #of rows for different flash sizes
Section10-1: Changed CPUCLK selectable options from n=0-5,7,8 to n=0-5,7
Clocks section: Changed ITMRCLK division to 1,2,3,4. updated the sources to
ITMRCLK, TCAPCLKs. Mentioned P17 is TTL enabled permanently. Corrected
FRT, PIT data write order. Updated INTCLR,INTMSK registers. in the register
table also. DC spec sheet: changed LVR to LVD included max min program-
mable trip points based on char data. Updated the 50ma sink pins on 638xx,
63903. Keep-alive voltage mentioned corresponding to Keep-alive current of
20uA. Included Notes regarding VOL,VOH on P1.0,P1.1 and TMDO spec. AC
Specs: T
MDO1
, T
SDO1
In description column changed Phase to 0
Rev.
ECN No.
Issue Date
Description of Change
BON
Section 5: Removed the VREG from the CY7C63310 and CY7C63801
Removed SCLK and SDATA. Created a separate pinout diagram for the
CY7C63813
Added the GPIO Block Diagram (
Figure 14-1.
)
Table 10-4
: Changed the Sleep Timer Clock unit from 32 KHz count to Hz
Table 21-1
: Added more descriptions to the register
Corrected V
TTL value in DC Characteristics table
Updated V
TTL value
Added footnote to pin description table for D+/D- pins
Added Typical Values to Low Voltage Detect table
Corrected Pin label on 16-pin PDIP package
Corrected minor typos
Corrected pin assignment for the 24-pin QSOP package - GPIO port 3 in Table
5-1: Pin Assignment
New Assignments: Pin 19 assigned to P3.0 and pin 20 to P3.1
Table 17.7 INT_MASK1 changed to 0xE1
Table 17.8 INT_MASK0 changed to 0xE0
Table 24.0-Register Summary, address E0 assigned to INT_MASK0 and
address E1 assigned to INT_MASK1
Minor text changes to make document more readable
Removed CY7C639xx
Removed CY7C639xx from Ordering Information Table
Added text concerning current draw for P0.0 and P0.1 in Table 5-1
Corrected Figure 9-2 to represent single stack
Added comment about availability of 3.3V I/O on P1.3-P1.6 in Table 5-1
Added information on Flash endurance and data retention to section 9.3
Added block diagrams and timing diagrams
Added CY7C638xx die form diagrams, Pad assignment tables and Ordering
information
Keyboard references removed
CY7C63923-XC die diagram removed, removed references to the 639xx parts
Updated part numbers in the header
*E
341277
See ECN
BHA
*F
408017
See ECN
TYJ
*G
424790
See ECN
TYJ
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C63801-PXC 功能描述:USB 接口集成電路 4K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63801-SXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 4K/256 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63801-SXCES 制造商:Cypress Semiconductor 功能描述:
CY7C638034-LQXC 功能描述:IC USB CONTROLLER RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A
CY7C638034-SXC 功能描述:IC USB CONTROLLERS RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A
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