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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 11 of 74
8.0
Instruction Set Summary
The instruction set is summarized in
Table 8-1
numerically and
serves as a quick reference. If more information is needed, the
Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order
[2, 3]
Instruction Set Summary tables are described in detail in the
PSoC Designer Assembly Language User Guide
(available on
the www.cypress.com web site).
O
00 15
01
02
03
04
05
06
07 10
08
09
0A
0B
0C
0D
0E
0F 10
10
11
12
13
14
15
16
17 10
18
19
1A
1B
1C
1D
1E
1F 10
20
21
22
23
24
25
26
27 10
28 11
29
2A
2B
2C
C
B
Instruction Format
1 SSC
2 ADD A, expr
2 ADD A, [expr]
2 ADD A, [X+expr]
2 ADD [expr], A
2 ADD [X+expr], A
3 ADD [expr], expr
3 ADD [X+expr], expr
1 PUSH A
2 ADC A, expr
2 ADC A, [expr]
2 ADC A, [X+expr]
2 ADC [expr], A
2 ADC [X+expr], A
3 ADC [expr], expr
3 ADC [X+expr], expr
1 PUSH X
2 SUB A, expr
2 SUB A, [expr]
2 SUB A, [X+expr]
2 SUB [expr], A
2 SUB [X+expr], A
3 SUB [expr], expr
3 SUB [X+expr], expr
1 POP A
2 SBB A, expr
2 SBB A, [expr]
2 SBB A, [X+expr]
2 SBB [expr], A
2 SBB [X+expr], A
3 SBB [expr], expr
3 SBB [X+expr], expr
1 POP X
2 AND A, expr
2 AND A, [expr]
2 AND A, [X+expr]
2 AND [expr], A
2 AND [X+expr], A
3 AND [expr], expr
3 AND [X+expr], expr
1 ROMX
2 OR A, expr
2 OR A, [expr]
2 OR A, [X+expr]
2 OR [expr], A
Flags
O
2D
2E
2F 10
30
31
32
33
34
35
36
37 10
38
39
3A
3B
3C
3D
3E 10
3F 10
40
41
42 10
43
44 10
45
46 10
47
48
49
4A 10
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
C
B
Instruction Format
2 OR [X+expr], A
3 OR [expr], expr
3 OR [X+expr], expr
1 HALT
2 XOR A, expr
2 XOR A, [expr]
2 XOR A, [X+expr]
2 XOR [expr], A
2 XOR [X+expr], A
3 XOR [expr], expr
3 XOR [X+expr], expr
2 ADD SP, expr
2 CMP A, expr
2 CMP A, [expr]
2 CMP A, [X+expr]
3 CMP [expr], expr
3 CMP [X+expr], expr
2 MVI A, [ [expr]++]
2 MVI [ [expr]++], A
1 NOP
3 AND reg[expr], expr
3 AND reg[X+expr], expr
3 OR reg[expr], expr
3 OR reg[X+expr], expr
3 XOR reg[expr], expr
3 XOR reg[X+expr], expr
3 TST [expr], expr
3 TST [X+expr], expr
3 TST reg[expr], expr
3 TST reg[X+expr], expr
1 SWAP A, X
2 SWAP A, [expr]
2 SWAP X, [expr]
1 SWAP A, SP
1 MOV X, SP
2 MOV A, expr
2 MOV A, [expr]
2 MOV A, [X+expr]
2 MOV [expr], A
2 MOV [X+expr], A
3 MOV [expr], expr
3 MOV [X+expr], expr
2 MOV X, expr
2 MOV X, [expr]
2 MOV X, [X+expr]
Flags
O
5A
5B
5C
5D
5E
5F 10
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C 13
7D
7E 10
7F
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx 13
C
B
Instruction Format
2 MOV [expr], X
1 MOV A, X
1 MOV X, A
2 MOV A, reg[expr]
2 MOV A, reg[X+expr]
3 MOV [expr], [expr]
2 MOV reg[expr], A
2 MOV reg[X+expr], A
3 MOV reg[expr], expr
3 MOV reg[X+expr], expr
1 ASL A
2 ASL [expr]
2 ASL [X+expr]
1 ASR A
2 ASR [expr]
2 ASR [X+expr]
1 RLC A
2 RLC [expr]
2 RLC [X+expr]
1 RRC A
2 RRC [expr]
2 RRC [X+expr]
2 AND F, expr
2 OR F, expr
2 XOR F, expr
1 CPL A
1 INC A
1 INC X
2 INC [expr]
2 INC [X+expr]
1 DEC A
1 DEC X
2 DEC [expr]
2 DEC [X+expr]
3 LCALL
3 LJMP
1 RETI
1 RET
2 JMP
2 CALL
2 JZ
2 JNZ
2 JC
2 JNC
2 JACC
2 INDEX
Flags
8
9
Z
Z
Z
5
4
4
6
7
4
6
7
7
8
9
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
9
4
6
7
7
8
9
Z
Z
Z
Z
Z
Z
Z
Z
Z
5
6
8
9
4
7
8
4
7
8
4
7
8
4
7
8
4
4
4
4
4
4
7
8
4
4
7
8
4
4
6
7
7
8
9
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
5
5
7
8
8
9
if (A=B) Z=1
if (A<B) C=1
4
4
6
7
7
8
9
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
4
9
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
9
5
4
6
7
7
8
9
9
8
9
9
5
7
7
5
4
4
5
6
5
6
8
9
4
6
7
5
4
6
7
7
8
9
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
7
C, Z
8
5
11
5
5
5
5
7
4
6
7
7
Z
Notes
2.
3.
Interrupt routines take 13 cycles before execution resumes at interrupt vector table.
The number of cycles required by an instruction is increased by one for instructions that span 256-byte boundaries in the Flash memory space.