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參數(shù)資料
| 型號(hào)： | CY7C63813 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| 中文描述： | enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器） |
| 文件頁數(shù)： | 21/74頁 |
| 文件大小： | 1441K |
| 代理商： | CY7C63813 |
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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 21 of 74
Table 10-4. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
No Buzz
Sleep Timer [1:0]
CPU Speed [2:0]
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:6]:
Reserved
Bit 5:
No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—
Table 11-1
), the LVD and POR detection circuit is turned on
periodically to detect any POR and LVD events on the V
pin (the Sleep Duty Cycle bits in the ECO_TR are used to control
the duty cycle—
Table 13-3
). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the LVD and
POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR event during
sleep at the expense of a slightly higher than average sleep current
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled
Note:
The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below
Bit [4:3]:
Sleep Timer [1:0]
Note:
Sleep intervals are approximate
Bit [2:0]:
CPU Speed [2:0]
The enCoRe II may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements
apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20
MHz. If the CPU speed register’s value is 0b011, the CPU clock will be 20 MHz. Therefore the supply voltage requirements for
the device are the same as if the part was operating at 24 MHz. The operating voltage requirements are not relaxed until the
CPU speed is at 12 MHz or less
Important Note:
Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the
two clocks have the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks have
different sources, care must be taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8 across
the full specification range of both clock sources
Sleep Timer
[1:0]
00
01
10
11
Sleep Timer Clock
Frequency (Nominal)
512 Hz
64 Hz
8 Hz
1 Hz
Sleep Period
(Nominal)
1.95 ms
15.6 ms
125 ms
1 sec
Watchdog Period
(Nominal)
6 ms
47 ms
375 ms
3 sec
CPU Speed
[2:0]
000
001
010
011
100
101
110
111
CPU when Internal
Oscillator is selected
3 MHz (Default)
6 MHz
12 MHz
24 MHz
1.5 MHz
750 KHz
187 KHz
Reserved
External Clock
Clock In/8
Clock In/4
Clock In/2
Clock In/1
Clock In/16
Clock In/32
Clock In/128
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63813-PXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 18-PDIP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63813-PXCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C63813-SXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 18-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63813-SXCES | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C63823-3XWC | 制造商:Cypress Semiconductor 功能描述:USB - Bulk 制造商:Cypress Semiconductor 功能描述:Bulk / USB Low-Speed Peripherals |
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