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參數(shù)資料
| 型號(hào)： | CY7C63823 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| 中文描述： | enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器） |
| 文件頁(yè)數(shù)： | 31/74頁(yè) |
| 文件大?。?/td> | 1441K |
| 代理商： | CY7C63823 |
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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 31 of 74
14.2
All the GPIO configuration registers have common configu-
ration controls. The following are the bit definitions of the GPIO
configuration registers
GPIO Port Configuration
14.2.1
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the
pin is configured for input or output. All interrupts are edge
Int Enable
sensitive, however for any interrupt that is shared by multiple
sources (i.e., Ports 2, 3, and 4) all inputs must be deasserted
before a new interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the
interrupt on the pin and then to generate the interrupt by
driving the appropriate pin state. This is useful in test and may
have value in applications as well.
Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
P1.1/D–
P1.0/D+
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins.
Bit 7:
P1.7 Data
P1.7 only exists in the CY7C638xx
Bit [6:3]:
P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
Beside their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternate function as the SPI interface pins. To
configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (
Table 14-13
)
The use of the pins as the P1.6–P1.3 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit 2:
P1.2/VREG
On the CY7C638(2/3)3, this pin can be used as the P1.2 GPIO or the VREG output. If the VREG output is enabled (Bit 0
Table 19-1
is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled
On the CY7C63813, this pin can only be used as the VREG output when USB mode is enabled. In non-USB mode, this pin can
be used as the P1.2 GPIO. The VREG functionality is not present in the CY7C63310 and the CY7C63801 variants. A 1
μ
F min,
2
μ
F max capacitor is required on VREG output.
Bit [1:0]:
P1.1–P1.0/D– and D+
When USB mode is disabled (Bit 7 in
Table 21-1
is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and
P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins respectively. If the USB
Force State bit (Bit 0 in
Table 18-1
) is set, the state of the D– and D+ pins can be controlled by writing to the D– and D+ bits
Table 14-3. P2 Data Register (P2DATA) [0x02] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
P2.1–P2.0
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bit [7:2]:
Reserved Data [7:2]
Bit [1:0]:
P2 Data [1:0]
P2.1–P2.0 only exist in the CY7C638(2/3)3
Table 14-4. P3 Data Register (P3DATA) [0x03] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
P3.1–P3.0
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 3 pins
Bit [7:2]:
Reserved Data [7:2]
Bit [1:0]:
P3 Data [1:0]
P3.1–P3.0 only exist in the CY7C638(2/3)3
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PDF描述 |
|---|---|
| CY7C63813 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63833 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63823-3XWC | 制造商:Cypress Semiconductor 功能描述:USB - Bulk 制造商:Cypress Semiconductor 功能描述:Bulk / USB Low-Speed Peripherals |
| CY7C638234-SXC | 功能描述:IC USB CONTROLLERS RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| CY7C638235-SXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C63823-PXC | 功能描述:IC USB PERIPHERAL CTRLR 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:CY7C 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| CY7C63823-QXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 24-QSOP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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