參數(shù)資料
型號(hào): CY7C63823
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述: enCoRe II還低速USB外設(shè)控制器(enCoRe II還低速的USB外設(shè)控制器)
文件頁(yè)數(shù): 33/74頁(yè)
文件大小: 1441K
代理商: CY7C63823
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 33 of 74
Table 14-5. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
Pull-up Enable
Output Enable
Read/Write
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled
the settings of this register are ignored
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts.
In the CY7C638xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit
Table 14-6. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Bit #
7
6
5
4
3
2
1
0
Field
CLK Output
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
Pull-up Enable
Output Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This pin is shared between the P0.1 GPIO use and the CLKOUT pin. When CLK output is set, the internally selected clock is
sent out onto P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts. In the CY7C638xx, only 8 mA sink drive capability
is available on this pin regardless of the setting of the High Sink bit
Bit 7:
CLK Output
0 = The clock output is disabled
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register—
Table 10-7
) is driven out to the pin
Table 14-7. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Act Low
TTL Thresh
Reserved
Open Drain
Pull-up Enable
Output Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
These registers control the operation of pins P0.2–P0.4 respectively. These pins are shared between the P0.2–P0.4 GPIOs and
the INT0–INT2. These registers exist in all enCoRe II parts. The INT0–INT2 interrupts are different than all the other GPIO
interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent
interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set.
These pins are enabled as interrupt sources in the interrupt controller registers (
Table 17-8
and
Table 17-6
).
To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2
pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the
P0.2, P0.3 and P0.4 data bits in the P0 Data Register
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and
Pull-up Enable bits control the behavior of the pin
The P0.2/INT0–P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09) respec-
tively.
Note:
Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these
interrupt sources, it is best to follow the following procedure:
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
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參數(shù)描述
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