參數(shù)資料
型號(hào): CY7C63823
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述: enCoRe II還低速USB外設(shè)控制器(enCoRe II還低速的USB外設(shè)控制器)
文件頁(yè)數(shù): 48/74頁(yè)
文件大?。?/td> 1441K
代理商: CY7C63823
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 48 of 74
17.5.1
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interrupt sources’ ability to create pending inter-
rupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3) which may be
referred to in general as INT_MSKx. If cleared, each bit in an
INT_MSKx register prevents a posted interrupt from becoming
a pending interrupt (input to the priority encoder). However, an
interrupt can still post even if its mask bit is zero. All INT_MSKx
bits are independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that will become a
pending interrupt.
Interrupt Mask Registers
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to
an INT_CLRx register, when ENSWINT is cleared, will cause
the corresponding interrupt to clear. If the ENSWINT bit is set,
any 0s written to the INT_CLRx registers are ignored.
However, 1s written to an INT_CLRx register, while ENSWINT
is set, will cause an interrupt to post for the corresponding
interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level inter-
actions that are sometimes necessary to create a hardware-
only interrupt.
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a 57‘1’ to the bits AND to the
ENSWINT (Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt
Table 17-4. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
GPIO Port 3
GPIO Port 2
PS/2 Data Low
INT2
16-bit Counter
Wrap
TCAP1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt
Table 17-3. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
(continued)
Table 17-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
ENSWINT
Reserved
Read/Write
R/W
Default
0
0
0
0
0
0
0
0
Bit 7:
Enable Software Interrupt (ENSWINT)
0= Disable. Writing 0s to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear
1= Enable. Writing 1s to an INT_CLRx register, when ENSWINT is set, will cause the corresponding interrupt to post.
Bit [6:0]:
Reserved
Table 17-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
GPIO Port 3
Int Enable
GPIO Port 2
Int Enable
PS/2 Data Low
Int Enable
INT2
Int Enable
16-bit Counter
Wrap Int Enable
TCAP1
Int Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
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CY7C63823-PXC 功能描述:IC USB PERIPHERAL CTRLR 24-DIP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:CY7C 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN(6x6) 包裝:* 其它名稱(chēng):Q6396337A
CY7C63823-QXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 24-QSOP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20