參數(shù)資料
型號: CY7C63823
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設控制器)
中文描述: enCoRe II還低速USB外設控制器(enCoRe II還低速的USB外設控制器)
文件頁數(shù): 5/74頁
文件大?。?/td> 1441K
代理商: CY7C63823
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 5 of 74
5.1
Pinouts Assignments
Table 5-1. Pin Assignments
32
QFN
24
QSOP
24
SOIC
18
SIOC
18
PDIP
16
SOIC
16
PDIP
Name
Description
21
22
19
20
18
19
P3.0
P3.1
GPIO Port 3 – configured as a group (byte)
9
8
11
10
11
10
P2.0
P2.1
GPIO Port 2 – configured as a group (byte)
14
14
13
10
15
9
13
P1.0/D+
GPIO Port 1 bit 0/USB D+
[1]
If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
GPIO Port 1 bit 1/USB D–
[1]
If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
P1.2/VREG GPIO Port 1 bit 2—Configured individually.
3.3V if regulator is enabled. (The 3.3V regulator is not
available in the CY7C63310 and CY7C63801.) A 1-
μ
F
min, 2-
μ
F max capacitor is required on Vreg output.
P1.3/SSEL GPIO Port 1 bit 3—Configured individually.
Alternate function is SSEL signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.4/SCLK GPIO Port 1 bit 4—Configured individually.
Alternate function is SCLK signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.5/SMOSI GPIO Port 1 bit 5—Configured individually.
Alternate function is SMOSI signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.6/SMISO GPIO Port 1 bit 6—Configured individually.
Alternate function is SMISO signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.7
GPIO Port 1 bit 7—Configured individually.
TTL voltage threshold.
P0.0
GPIO Port 0 bit 0—Configured individually.
On CY7C638xx and CY7C63310, external clock
input when configured as Clock In.
P0.1
GPIO Port 0 bit 1—Configured individually
On CY7C638xx and CY7C63310, clock output when
configured as Clock Out.
P0.2/INT0
GPIO port 0 bit 2—Configured individually
Optional rising edge interrupt INT0
P0.3/INT1
GPIO port 0 bit 3—Configured individually
Optional rising edge interrupt INT1
P0.4/INT2
GPIO port 0 bit 4—Configured individually
Optional rising edge interrupt INT2
15
15
14
11
16
10
14
P1.1/D–
18
17
16
13
18
12
16
20
18
17
14
1
13
1
23
21
20
15
2
14
2
24
22
21
16
3
15
3
25
23
22
17
4
16
4
26
24
23
18
5
7
9
9
8
13
7
11
6
8
8
7
12
6
10
5
7
7
6
11
5
9
4
6
6
5
10
4
8
3
5
5
4
9
3
7
Note
1.
P1.0(D+) and P1.1(D-) pins must be in I/O mode when used as GPIO and in I
sb
mode.
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相關代理商/技術參數(shù)
參數(shù)描述
CY7C63823-3XWC 制造商:Cypress Semiconductor 功能描述:USB - Bulk 制造商:Cypress Semiconductor 功能描述:Bulk / USB Low-Speed Peripherals
CY7C638234-SXC 功能描述:IC USB CONTROLLERS RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN(6x6) 包裝:* 其它名稱:Q6396337A
CY7C638235-SXC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C63823-PXC 功能描述:IC USB PERIPHERAL CTRLR 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:CY7C 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN(6x6) 包裝:* 其它名稱:Q6396337A
CY7C63823-QXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 24-QSOP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20