參數(shù)資料
型號: CY7C63833
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述: enCoRe II還低速USB外設(shè)控制器(enCoRe II還低速的USB外設(shè)控制器)
文件頁數(shù): 13/74頁
文件大小: 1441K
代理商: CY7C63833
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 13 of 74
9.2
The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM.
Data Memory Organization
9.3
This section describes the Flash block of the enCoRe II. Much
of the user-visible Flash functionality including programming
and security are implemented in the M8C Supervisory Read
Only Memory (SROM). enCoRe II Flash has an endurance of
1000 cycles and a 10 year data retention capability.
Flash
9.3.1
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visible
to the M8C CPU when it is executing out of SROM. This makes
it impossible to read, write or erase the Flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can only program the Flash via SROM
calls. The data or code images can be sourced via any
interface with the appropriate support firmware. This type of
programming requires a ‘boot-loader’—a piece of firmware
resident on the Flash. For safety reasons this boot-loader must
not be overwritten during firmware rewrites.
The Flash provides four extra auxiliary rows that are used to
hold Flash block protection flags, boot time calibration values,
configuration tables, and any device values. The routines for
accessing these auxiliary rows are documented in the SROM
section. The auxiliary rows are not affected by the device
erase function.
Flash Programming and Security
9.3.2
Most designs that include an enCoRe II part will have a USB
connector attached to the USB D+/D– pins on the device.
These designs require the ability to program or reprogram a
part through these two pins alone.
enCoRe II devices enable this type of in-system programming
by using the D+ and D– pins as the serial programming mode
interface. This allows an external controller to cause the
enCoRe II part to enter serial programming mode and then to
In-System Programming
use the test queue to issue Flash access functions in the
SROM. The programming protocol is not USB.
9.4
The SROM holds code that is used to boot the part, calibrate
circuitry, and perform Flash operations. (
Table 9-1
lists the
SROM functions.) The functions of the SROM may be
accessed in normal user code or operating from Flash. The
SROM exists in a separate memory space from user code.
The SROM functions are accessed by executing the Super-
visory System Call instruction (SSC), which has an opcode of
00h. Prior to executing the SSC the M8C’s accumulator needs
to be loaded with the desired SROM function code from
Table 9-1
. Undefined functions will cause a HALT if called from
user code. The SROM functions are executing code with calls;
therefore, the functions require stack space. With the
exception of Reset, all of the SROM functions have a
parameter block
in SRAM that must be configured before
executing the SSC.
Table 9-2
lists all possible parameter block
variables. The meaning of each parameter, with regards to a
specific SROM function, is described later in this chapter.
SROM
Figure 9-2. Data Memory Organization
after reset
8-bit PSP
Address
0x00
Stack begins here and grows upward.
Top of RAM Memory
0xFF
Table 9-1. SROM Function Codes
Function Code
00h
01h
02h
03h
05h
06h
07h
Function Name
SWBootReset
ReadBlock
WriteBlock
EraseBlock
EraseAll
TableRead
CheckSum
Stack Space
0
7
10
9
11
3
3
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