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參數(shù)資料
| 型號(hào)： | CY7C63833 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| 中文描述： | enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器） |
| 文件頁數(shù)： | 36/74頁 |
| 文件大?。?/td> | 1441K |
| 代理商： | CY7C63833 |
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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 36 of 74
15.0
Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, making its functionality independent of system clock
speed. SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
15.1
SPI Data Register
When an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty,
firmware has 7 SPI clocks to manage the buffers—to empty the receiver buffer, or to refill the transmit holding register. Failure to
meet this timing requirement will result in incorrect data transfer.
Table 14-16. P2 Configuration (P2CR) [0x15] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
Pull-up Enable
Output Enable
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register only exists in CY7C638xx. This register controls the operation of pins P2.0–P2.1. In the CY7C638xx, only 8 mA
sink drive capability is available on this pin regardless of the setting of the High Sink bit
Table 14-17. P3 Configuration (P3CR) [0x16] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
Pull-up Enable
Output Enable
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
1
0
This register exists in CY7C638xx. This register controls the operation of pins P3.0–P3.1.
In the CY7C638xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit
Table 15-1. SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPIData[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
Bit [7:0]:
SPI Data [7:0]
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| CY7C65640 | TetraHub High-speed USB Hub Controller |
| CY7C65640-LFC | TetraHub High-speed USB Hub Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C638334-LTXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C638335-LFXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C638335-LTXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C63833-LFXC | 功能描述:USB 接口集成電路 8K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63833-LTXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 32-QFN RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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