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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 40 of 74
Table 16-2. Free-running Timer High-order Byte (FRTMRH) [0x21] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Free-running Timer [15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Free-running Timer [15:8]
When reading the Free-running Timer, the low-order byte must be read first and the high-order second. When writing, the low-
order byte must be written first then the high-order byte
Table 16-3. Timer Capture 0 Rising (TCAP0R) [0x22] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Capture 0 Rising [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Capture 0 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TCAP0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer
Table 16-4. Timer Capture 1 Rising (TCAP1R) [0x23] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Capture 1 Rising [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Capture 1 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TCAP1 input. The bits that are
stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in 16-bit mode this
register holds the high-order 8 bits of the 16-bit timer from the last Capture 0 rising edge. When Capture 0 is in 16-bit mode this
register will be loaded with high-order 8 bits of the 16-bit timer on TCAP0 rising edge
Table 16-5. Timer Capture 0 Falling (TCAP0F) [0x24] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Capture 0 Falling [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Capture 0 Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TCAP0 input. When Capture
0 is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower-order 8 bits of the 16-bit timer
Table 16-6. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Capture 1 Falling [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Capture 1Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TCAP1 input. The bits that
are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in 16-bit mode this
register holds the high-order 8 bits of the 16-bit timer from the last Capture 0 falling edge. When Capture 0 is in 16-bit mode this
register will be loaded with high-order 8 bits of the 16-bit timer on TCAP0 falling edge