參數(shù)資料
型號(hào)： CY7C63833
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁(yè)數(shù)： 5/74頁(yè)
文件大?。?/td> 1441K
代理商： CY7C63833
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 5 of 74
5.1
Pinouts Assignments
Table 5-1. Pin Assignments
32
QFN
24
QSOP
24
SOIC
18
SIOC
18
PDIP
16
SOIC
16
PDIP
Name
Description
21
22
19
20
18
19
P3.0
P3.1
GPIO Port 3 – configured as a group (byte)
9
8
11
10
11
10
P2.0
P2.1
GPIO Port 2 – configured as a group (byte)
14
14
13
10
15
9
13
P1.0/D+
GPIO Port 1 bit 0/USB D+
[1]
If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
GPIO Port 1 bit 1/USB D–
[1]
If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
P1.2/VREG GPIO Port 1 bit 2—Configured individually.
3.3V if regulator is enabled. (The 3.3V regulator is not
available in the CY7C63310 and CY7C63801.) A 1-
μ
F
min, 2-
μ
F max capacitor is required on Vreg output.
P1.3/SSEL GPIO Port 1 bit 3—Configured individually.
Alternate function is SSEL signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.4/SCLK GPIO Port 1 bit 4—Configured individually.
Alternate function is SCLK signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.5/SMOSI GPIO Port 1 bit 5—Configured individually.
Alternate function is SMOSI signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.6/SMISO GPIO Port 1 bit 6—Configured individually.
Alternate function is SMISO signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
P1.7
GPIO Port 1 bit 7—Configured individually.
TTL voltage threshold.
P0.0
GPIO Port 0 bit 0—Configured individually.
On CY7C638xx and CY7C63310, external clock
input when configured as Clock In.
P0.1
GPIO Port 0 bit 1—Configured individually
On CY7C638xx and CY7C63310, clock output when
configured as Clock Out.
P0.2/INT0
GPIO port 0 bit 2—Configured individually
Optional rising edge interrupt INT0
P0.3/INT1
GPIO port 0 bit 3—Configured individually
Optional rising edge interrupt INT1
P0.4/INT2
GPIO port 0 bit 4—Configured individually
Optional rising edge interrupt INT2
15
15
14
11
16
10
14
P1.1/D–
18
17
16
13
18
12
16
20
18
17
14
1
13
1
23
21
20
15
2
14
2
24
22
21
16
3
15
3
25
23
22
17
4
16
4
26
24
23
18
5
7
9
9
8
13
7
11
6
8
8
7
12
6
10
5
7
7
6
11
5
9
4
6
6
5
10
4
8
3
5
5
4
9
3
7
Note
1.
P1.0(D+) and P1.1(D-) pins must be in I/O mode when used as GPIO and in I
sb
mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C638334-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LFXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C63833-LFXC 功能描述:USB 接口集成電路 8K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63833-LTXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 32-QFN RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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