參數(shù)資料
型號： CY7C63833
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁數(shù)： 6/74頁
文件大?。?/td> 1441K
代理商： CY7C63833
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 6 of 74
6.0
CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard-architecture microprocessor. Five registers
control the primary operation of the CPU core. These registers
are affected by various instructions, but are not directly acces-
sible through the register space by the user.
The 16-bit Program Counter Register (CPU_PC) allows for
direct addressing of the full eight Kbytes of program memory
space.
The Accumulator Register (CPU_A) is the general-purpose
register that holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by
the SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable
interrupts. The user cannot manipulate the Supervisory State
status bit [3]. The flags are affected by arithmetic, logic, and
shift operations. The manner in which each flag is changed is
dependent upon the instruction being executed (i.e., AND,
OR, XOR). See
Table 8-1
.
2
4
4
3
8
2
6
P0.5/TIO0
GPIO port 0 bit 5—Configured individually
Alternate function Timer capture inputs or Timer
output TIO0
GPIO port 0 bit 6—Configured individually
Alternate function Timer capture inputs or Timer
output TIO1
GPIO port 0 bit 7—Configured individually
Not present in the 16 pin PDIP or SOIC package
1
3
3
2
7
1
5
P0.6/TIO1
32
2
2
1
6
P0.7
10
11
12
17
19
27
28
29
30
31
16
13
1
12
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vcc
V
SS
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
Supply
Ground
24
16
13
15
12
12
9
17
14
11
8
15
12
Table 5-1. Pin Assignments
(continued)
32
QFN
24
QSOP
24
SOIC
18
SIOC
18
PDIP
16
SOIC
16
PDIP
Name
Description
Table 6-1. CPU Registers and Register Names
Register
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
CPU_X
Flags
Program Counter
Accumulator
Stack Pointer
Index
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C638334-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LFXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C63833-LFXC 功能描述:USB 接口集成電路 8K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63833-LTXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 32-QFN RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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