參數(shù)資料
型號： CY7C67200
廠商： Cypress Semiconductor Corp.
英文描述： EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器)
中文描述： 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器）
文件頁數(shù)： 14/82頁
文件大小： 1719K
代理商： CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 14 of 82
minimal, but in applications that are very CPU intensive the
incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is
triggered. Upon exiting the HALT state, one or two instructions
immediately following the HALT instruction may get executed
before the waking interrupt is serviced (you may want to follow
the HALT instruction with two NOPs).
1:
Enable Halt Mode
0:
No Function
Reserved
All reserved bits must be written as ‘0’.
8.1.6
Interrupt Enable Register [0xC00E] [R/W]
Figure 8-7. Interrupt Enable Register
Register Description
The Interrupt Enable Register allows control of the hardware
interrupt vectors.
OTG Interrupt Enable
(Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG
ID/OTG4.4V Valid hardware interrupt.
1:
Enable OTG interrupt
0:
Disable OTG interrupt
SPI Interrupt Enable
(Bit 11)
The SPI Interrupt Enable bit enables or disables the following
three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA
Block Done.
1:
Enable SPI interrupt
0:
Disable SPI interrupt
Host/Device 2 Interrupt Enable
(Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all
of the following Host/Device 2 hardware interrupts: Host 2
USB
Done,
Host
2
USB
WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP
or WakeUp from USB, Device 2 Endpoint n.
1:
Enable Host 2 and Device 2 interrupt
0:
Disable Host 2 and Device 2 interrupt
SOF/EOP,
Host
2
Host/Device 1 Interrupt Enable
(Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all
of the following Host/Device 1 hardware interrupts: Host 1
USB
Done,
Host
1
USB
WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP
or WakeUp from USB, Device 1 Endpoint n.
1:
Enable Host 1 and Device 1 interrupt
0:
Disable Host 1 and Device 1 interrupt
SOF/EOP,
Host
1
HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following
High-speed Serial Interface hardware interrupts: HSS Block
Done, and HSS RX Full.
1:
Enable HSS interrupt
0:
Disable HSS interrupt
In Mailbox Interrupt Enable
(Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the
HPI: Incoming Mailbox hardware interrupt.
1:
Enable MBXI interrupt
0:
Disable MBXI interrupt
Out Mailbox Interrupt Enable
(Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the
HPI: Outgoing Mailbox hardware interrupt.
1:
Enable MBXO interrupt
0:
Disable MBXO interrupt
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
OTG
Interrupt
Enable
SPI
Interrupt
Enable
Reserved
Host/Device 2
Interrupt
Enable
Host/Device 1
Interrupt
Enable
Read/Write
-
-
-
R/W
R/W
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
HSS
Interrupt
Enable
In Mailbox
Interrupt
Enable
Out Mailbox
Interrupt
Enable
Reserved
UART
Interrupt
Enable
GPIO
Interrupt
Enable
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Default
0
0
0
1
0
0
0
0
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CY7C672001-48BAXIT 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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