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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機/外設控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設備控制器） |
| 文件頁數(shù)： | 16/82頁 |
| 文件大?。?/td> | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 16 of 82
8.1.8
USB Diagnostic Register [0xC03C] [R/W]
Figure 8-9. USB Diagnostic Register
Register Description
The USB Diagnostic Register provides control of diagnostic
modes. It is intended for use by device characterization tests,
not for normal operations. This register is Read/Write by the
on-chip CPU but is write only via the HPI port.
Port 2A Diagnostic Enable
(Bit 15)
The Port 2A Diagnostic Enable bit enables or disables Port 2A
for the test conditions selected in this register.
1:
Apply any of the following enabled test conditions: J/K,
DCK, SE0, RSF, RSL, PRD
0:
Do not apply test conditions
Port 1A Diagnostic Enable
(Bit 15)
The Port 1A Diagnostic Enable bit enables or disables Port 1A
for the test conditions selected in this register.
1:
Apply any of the following enabled test conditions: J/K,
DCK, SE0, RSF, RSL, PRD
0:
Do not apply test conditions
Pull-down Enable
(Bit 6)
The Pull-down Enable bit enables or disables full-speed pull
down resistors (pull down on both D+ and D–) for testing.
1:
Enable pull down resistors on both D+ and D–
0:
Disable pull down resistors on both D+ and D–
LS Pull-up Enable
(Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull
up resistor (pull up on D–) for testing.
1:
Enable low-speed pull up resistor on D–
0:
Pull-up resistor is not connected on D–
FS Pull-up Enable
(Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull
up resistor (pull up on D+) for testing.
1:
Enable full-speed pull up resistor on D+
0:
Pull-up resistor is not connected on D+
Force Select
(Bits [2:0])
The Force Select field bit selects several different test
condition states on the data lines (D+/D–). See
Table 8-3
for
details.
Reserved
All reserved bits must be written as ‘0’.
8.2
There are three registers dedicated to timer operations. Each
of these registers are discussed in this section and are
summarized in
Figure 8-10
.
Timer Registers
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Port 2A
Diagnostic
Enable
Reserved
Port 1A
Diagnostic
Enable
Reserved...
Read/Write
-
R/W
-
R/W
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Pull-down
Enable
LS Pull-up
Enable
FS Pull-up
Enable
Reserved
Force Select
Read/Write
-
R/W
R/W
R/W
-
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Table 8-3. Force Select Definition
Force Select [2:0]
1xx
01x
001
000
Data Line State
Assert SE0
Toggle JK
Assert J
Assert K
Figure 8-10. Timer Registers
Register Name
Watchdog Timer Register
Timer 0 Register
Timer 1 Register
Address
0xC00C
0xC010
0xC012
R/W
R/W
R/W
R/W
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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