參數(shù)資料
型號(hào): CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁(yè)數(shù): 20/82頁(yè)
文件大?。?/td> 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 20 of 82
8.4
There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless
otherwise noted); one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized
in
Figure 8-15
.
USB Host Only Registers
8.4.1
Host 1 Control Register 0xC080
Host 2 Control Register 0xC0A0
Host n Control Register [R/W]
Figure 8-16. Host n Control Register
Register Description
The Host n Control register allows high-level USB transaction control.
Preamble Enable
(Bit 7)
The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should
only be set when communicating with a low-speed device.
1:
Enable Preamble packet
0:
Disable Preamble packet
Sequence Select
(Bit 6)
The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence
checking must be handled in firmware.
1:
Send DATA1
0:
Send DATA0
Figure 8-15. USB Host Only Register
Register Name
Host n Control Register
Host n Address Register
Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register
Host n Device Address Register
Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count Register
Host n SOF/EOP Counter Register
Host n Frame Register
Address (Host 1/Host 2)
0xC080/0xC0A0
0xC082/0xC0A2
0xC084/0xC0A4
0xC086/0xC0A6
0xC086/0xC0A6
0xC088/0xC0A8
0xC088/0xC0A8
0xC08C/0xC0AC
0xC090/0xC0B0
0xC092/0xC0B2
0xC094/0xC0B4
0xC096/0xC0B6
R/W
R/W
R/W
R/W
R
W
R
W
R/W
R/W
R/W
R
R
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Preamble
Enable
Sequence
Select
Sync
Enable
ISO
Enable
Reserved
Arm
Enable
Read/Write
R/W
R/W
R/W
R/W
-
-
-
R/W
Default
0
0
0
0
0
0
0
0
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