參數(shù)資料
型號(hào)： CY7C67200
廠商： Cypress Semiconductor Corp.
英文描述： EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述： 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器）
文件頁數(shù)： 5/82頁
文件大小： 1719K
代理商： CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 5 of 82
5.8
EZ-OTG has an HPI interface. The HPI interface provides
DMA access to the EZ-OTG internal memory by an external
host, plus a bidirectional mailbox register for supporting high-
level communication protocols. This port is designed to be the
primary high-speed connection to a host processor. Complete
control of EZ-OTG can be accomplished through this interface
via an extensible API and communication protocol. Other than
the hardware communication protocols, a host processor has
identical control over EZ-Host whether connecting to the HPI
or HSS port. The HPI interface is exposed through GPIO pins.
Note
It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as
outputs for a test mode. If these pins need to be used as inputs,
a series resistor is required (10 ohm - 48 ohm is recom-
mended). Refer to BIOS documentation for addition details.
See “Reset Pin” on page 9.
Host Port Interface (HPI)
5.8.1
16-bit data bus interface
16 MB/s throughput
Auto-increment of address pointer for fast block mode
transfers
Direct memory access (DMA) to internal memory
Bidirectional Mailbox register
Byte Swapping
Complete access to internal memory
Complete control of SIE’s through HPI
Dedicated HPI Status register
HPI Features
5.8.2
HPI Pins
The two HPI address pins are used to address one of four
possible HPI port registers as shown in
Table 5-10
below.
5.9
VBUS for the USB On-The-Go (OTG) port can be produced by
EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to the
diagram below.
Charge Pump Interface
Component details:
D1 and D2: Schottky diodes with a current rating greater
than 60 mA.
C1: Ceramic capacitor with a capacitance of 0.1 μF.
C2: Capacitor value must be no more that 6.5 μF since that
is the maximum capacitance allowed by the USB OTG
specification for a dual-role device. The minimum value of
C2 is 1 μF. There are no restrictions on the type of capacitor
for C2.
If the VBUS charge pump circuit is not to be used,
CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-
nected.
Notes:
1.
2.
HPI_INT is for the Outgoing Mailbox Interrupt.
HPI strobes are negative logic sampled on rising edge.
Table 5-9. HPI Interface Pins
[1, 2]
Pin Name
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
Pin Number
H4
G4
H5
G5
H6
F5
F6
E4
E5
E6
D4
D5
C6
C5
D7
D6
D5
D4
D3
D2
D1
D0
B5
B4
C4
B3
A3
C3
A2
B2
Table 5-10. HPI Addressing
HPI A[1:0]
HPI Data
HPI Mailbox
HPI Address
HPI Status
A1
0
0
1
1
A0
0
1
0
1
Figure 5-1. Charge Pump
Table 5-9. HPI Interface Pins
[1, 2]
(continued)
Pin Name
Pin Number
CSWITCHA
CY7C67200
CSWITCHB
OTGVBUS
D1
D2
C1
C2
VBUS
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CY7C672001-48BAXI 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C672001-48BAXIT 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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