參數(shù)資料
型號: CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器)
文件頁數(shù): 56/82頁
文件大?。?/td> 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 56 of 82
8.10
There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in
Figure 8-64
.
SPI Registers
8.10.1
SPI Configuration Register [0xC0C8] [R/W]
Figure 8-65. SPI Configuration Register
Register Description
The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
3Wire Enable
(Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.
1:
MISO and MOSI data lines are tied together
0:
Normal MISO and MOSI Full Duplex operation (not tied together)
Phase Select
(Bit 14)
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.
1:
Advanced SCK phase
0:
Delayed SCK phase
SCK Polarity Select
(Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1:
Positive SCK polarity
0:
Negative SCK polarity
Figure 8-64. SPI Registers
Register Name
Address
0xC0C8
0xC0CA
0xC0CC
0xC0CE
0xC0D0
0xC0D2
0xC0D4
0xC0D6
0xC0D8
0xC0DA
0xC0DC
0xC0DE
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPI Configuration Register
SPI Control Register
SPI Interrupt Enable Register
SPI Status Register
SPI Interrupt Clear Register
SPI CRC Control Register
SPI CRC Value
SPI Data Register
SPI Transmit Address Register
SPI Transmit Count Register
SPI Receive Address Register
SPI Receive Count Register
Bit #
15
14
13
12
11
10
9
8
Field
3Wire
Enable
Phase
Select
SCK Polarity
Select
Scale Select
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Default
1
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Master
Active Enable
Master
Enable
SS
Enable
SS Delay Select
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
1
1
1
1
1
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