參數(shù)資料
型號(hào): CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁數(shù): 7/82頁
文件大小: 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 7 of 82
5.11.1
Crystal Pins
5.12
EZ-OTG can boot into any one of four modes. The mode it
boots into is determined by the TTL voltage level of
GPIO[31:30] at the time nRESET is deasserted.
Table 5-14
shows the different boot pin combinations possible. After a
reset pin event occurs, the BIOS bootup procedure executes
for up to 3 ms. GPIO[31:30] are sampled by the BIOS during
bootup only. After bootup these pins are available to the appli-
cation as GPIO’s.
Boot Configuration Interface
GPIO[31:30] must be pulled high or low as needed using re-
sistors tied to VCC or GND with resistor values between 5K
ohm and 15K ohm. GPIO[31:30] must not be tied directly to
VCC or GND. Note that in Standalone mode, the pull ups on
those two pins are used for the serial I2C EEPROM (if imple-
mented). The resistors used for these pull ups must conform
to the serial EEPROM manufacturer's requirements.
If any mode other then standalone is chosen, EZ-OTG will be
in coprocessor mode. The device will power up with the appro-
priate communication interface enabled according to its boot
pins and wait idle until a coprocessor communicates with it.
See the BIOS documentation for greater detail on the boot
process.
5.13
There are two modes of operation: Coprocessor and
Standalone.
Operational Modes
5.13.1
EZ-OTG can act as a coprocessor to an external host
processor. In this mode, an external host processor drives EZ-
OTG and is the main processor rather then EZ-OTG’s own 16-
bit internal CPU. An external host processor may interface to
EZ-OTG through one of the following three interfaces in copro-
cessor mode:
HPI mode, a 16-bit parallel interface with up to 16 MBytes
transfer rate
HSS mode, a serial interface with up to 2M baud transfer
rate
SPI mode, a serial interface with up to 2 Mbits/s transfer
rate.
At bootup GPIO[31:30] determine which of these three inter-
faces are used for coprocessor mode. Refer to
Table 5-14
for
details. Bootloading begins from the selected interface after
POR + 3 ms of BIOS bootup.
Coprocessor Mode
5.13.2
In standalone mode, there is no external processor connected
to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an
EEPROM. Optionally, firmware may also be downloaded via
USB. Refer to
Table 5-14
for booting into standalone mode.
After booting into standalone mode (GPIO[31:30] = ‘11’), the
following pins are affected:
GPIO[31:30] are configured as output pins to examine the
EEPROM contents.
GPIO[28:27] are enabled for debug UART mode.
GPIO[29] is configured as OTGID for OTG applications on
PORT1A.
—If OTGID is logic 1 then PORT1A (OTG) is configured
as a USB peripheral.
—If OTGID is logic 0 then PORT1A (OTG) is configured
as a USB host.
Ports 1B, 2A, and 2B default as USB peripheral ports.
All other pins remain INPUT pins.
Standalone Mode
Table 5-13. Crystal Pins
Pin Name
XTALIN
XTALOUT
Pin Number
G3
G2
Table 5-14. Boot Configuration Interface
GPIO31
(Pin 39)
0
0
1
GPIO30
(Pin 40)
0
1
0
Boot Mode
Host Port Interface (HPI)
High Speed Serial (HSS)
Serial Peripheral Interface (SPI, slave
mode)
I2C EEPROM (Standalone Mode)
1
1
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