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參數資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機/外設控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設備控制器） |
| 文件頁數： | 8/82頁 |
| 文件大小： | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 8 of 82
5.13.2.1 Minimum Hardware Requirements for Standalone Mode – Peripheral Only
6.0
Power Savings and Reset Description
The EZ-OTG modes and reset conditions are described in this
section.
6.1
EZ-OTG has one main power savings mode, Sleep. For de-
tailed information on Sleep mode, see section 6.2.
Sleep mode is used for USB applications to support USB sus-
pend and non USB applications as the main chip power down
mode.
In addition, EZ-OTG is capable of slowing down the CPU clock
speed through the CPU Speed register [0xC008] without af-
fecting other peripheral timing. Reducing the CPU clock speed
from 48 MHz to 24 MHz reduces the overall current draw by
around 8 mA while reducing it from 48 MHz to 3 MHz reduces
the overall current draw by approximately 15 mA.
Power Savings Mode Description
6.2
Sleep mode is the main chip power down mode and is also
used for USB suspend. Sleep mode is entered by setting the
Sleep Enable (bit 1) of the Power Control register [0xC00A].
Sleep
During Sleep mode (USB Suspend) the following events and
states are true:
GPIO pins maintain their configuration during sleep (in
suspend).
External Memory Address pins are driven low.
XTALOUT is turned off.
Internal PLL is turned off.
Firmware must disable the charge pump (OTG Control
register [0xC098]) causing OTGVBUS to drop below 0.2V.
Otherwise OTGVBUS will only drop to V
CC
– (2 schottky
diode drops).
Booster circuit is turned off.
USB transceivers is turned off.
CPU suspends until a programmable wakeup event.
6.3
There are several possible events available to wake EZ-OTG
from Sleep mode as shown in
Table 6-1
. These may also be
used as remote wakeup options for USB applications. See
“Power Control Register [0xC00A] [R/W]” on page 13.
Upon wakeup, code begins executing within 200 ms, the time
it takes the PLL to stabilize.
External (Remote) Wakeup Source
Figure 5-5. Minimum Standalone Hardware Configuration – Peripheral Only
EZ-OTG
CY7C67200
GPIO[30]
GPIO[31]
SCL*
SDA*
10k
Bootstrap Options
Bootloading Firmware
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30] 31 30
Up to 2k x8 SCL SDA
>2k x8 to 64k x8 SDA SCL
Vcc
10k
Vcc
A2
GND
A0
A1
SCL
SDA
VCC
WP
VCC
Up to 64k x8
EEPROM
Int. 16k x8
Code / Data
XOUT
XIN
12MHz
22pf
22pf
nRESET
Reset
Logic
*Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
VCC, AVCC,
BoostVCC
VReg
DMinus
DPlus
Standard-B
or Mini-B
D+
D-
VBus
GND
SHIELD
Reserved
GND, AGND,
BoostGND
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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