參數(shù)資料
型號(hào)： CY7C67200
廠商： Cypress Semiconductor Corp.
英文描述： EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述： 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器）
文件頁(yè)數(shù)： 9/82頁(yè)
文件大?。?/td> 1719K
代理商： CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 9 of 82
6.4
The length of the power-on-reset event can be defined by
(VCC ramp to valid) + (Crystal start up). A typical application
might utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms,
respectively.
Power-On Reset (POR) Description
6.5
The Reset pin is active low and requires a minimum pulse
duration of sixteen 12-MHz clock cycles (1.3 ms). A reset
event restores all registers to their default POR settings. Code
execution then begins 200 ms later at 0xFF00 with an imme-
diate jump to 0xE000, the start of BIOS.
Note
It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as out-
puts for a test mode. If these pins need to be used as inputs,
a series resistor is required (10 ohm - 48 ohm is recommend-
ed). Refer to BIOS documentation for addition details.
Reset Pin
6.6
A USB Reset affects registers 0xC090 and 0xC0B0, all other
registers remain unchanged.
USB Reset
7.0
Memory Map
Memory map information is presented in this section.
7.1
The EZ-OTG has just over 24 KB of addressable memory
mapped from 0x0000 to 0xFFFF. This 24 KB contains both
program and data space and is byte addressable.
Figure 7-1
.
shows the various memory region address locations.
Mapping
7.2
Of the internal memory, 15 KB is allocated for user’s program
and data code. The lower memory space from 0x0000 to
0x04A2 is reserved for interrupt vectors, general purpose
registers, USB control registers, the stack, and other BIOS
variables. The upper internal memory space contains EZ-OTG
control registers from 0xC000 to 0xC0FF and the BIOS ROM
itself from 0xE000 to 0xFFFF. For more information on the
Internal Memory
reserved lower memory or the BIOS ROM, refer to the
Programmers documentation and the BIOS documentation.
During development with the EZ-OTG toolset, the lower area
of User's space (0x04A4 to 0x1000) should be left available to
load the GDB stub. The GDB stub is required to allow the
toolset debug access into EZ-OTG.
Notes:
3.
4.
Read data will be discarded (dummy data).
HPI_INT will assert on a USB Resume.registers
Table 6-1. wakeup Sources
[3, 4]
Wakeup Source (if enabled)
USB Resume
OTGVBUS
OTGID
HPI
HSS
SPI
IRQ0 (GPIO 24)
Event
D+/D- Signaling
Level
Any Edge
Read
Read
Read
Any Edge
HW INT's
SW INT's
0x0000 - 0x00FF
Primary Registers
Swap Registers
HPI Int / Mailbox
LCP Variables
USB Registers
Slave Setup Packet
BIOS Stack
USB Slave & OTG
BIOS
USER SPACE
~15K
Internal Memory
Control Registers
0x0100 - 0x011F
0x0120 - 0x013F
0x0140 - 0x0148
0x014A - 0x01FF
0x0200- 0x02FF
0x0300- 0x030F
0x0310- 0x03FF
0x0400- 0x04A2
0x04A4- 0x3FFF
0xC000- 0xC0FF
0xE000- 0xFFFF
Figure 7-1. Memory Map
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CY7C672001-48BAXIT 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C67200-48BAXI 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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CY7C67300-100AI 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC
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