參數(shù)資料
型號(hào): CY7C68300C
廠商: Cypress Semiconductor Corp.
英文描述: EZ-USB AT2LP USB 2.0 to ATA/ATAPI Bridge(EZ-USB AT2LP USB 2.0到ATA/ATAPI橋接器)
中文描述: 的EZ - USB AT2LP產(chǎn)品的USB 2.0的ATA / ATAPI橋(的EZ - USB AT2LP產(chǎn)品的USB 2.0到ATA / ATAPI接口橋接器)
文件頁數(shù): 10/42頁
文件大?。?/td> 761K
代理商: CY7C68300C
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A
Page 10 of 42
68
34
41
DA0
O/Z
[1]
Driven HIGH
after 2 ms
delay
Driven HIGH
after 2 ms
delay
Input
ATA address
.
69
35
42
DA1
O/Z
[1]
ATA address
.
70
[3]
36
[3]
43
DRVPWRVLD
(
DA2
)
I
Device presence detect.
(See
“DRVPWRVLD” on
page 13
). Configurable logical polarity is controlled by
EEPROM address 0x08. This pin must be pulled HIGH
if functionality is not utilized.
Alternate function.
Input when the EEPROM configu-
ration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 0).
ATA chip select
.
71
37
44
CS0#
O/Z
[1]
Driven HIGH
after 2 ms
delay
Driven HIGH
after 2 ms
delay
Driven HIGH
after 2 ms
delay
72
38
45
CS1#
O/Z
[1]
ATA chip select
.
73
39
46
DA2
(
VBUS_PWR_VALID
)
O/Z
[1]
ATA address
.
74
75
76
77
78
79
40
41
N/A
42
43
44
47
48
N/A
49
50
51
ARESET#
GND
NC
RESET#
V
CC
O/Z
[1]
GND
NC
I
PWR
I
ATA reset
.
Ground
.
No connect
.
Chip reset
(See
“RESET#” on page 14
).
V
CC
. Connect to 3.3V power source.
VBUS detection
(See
“VBUS_ATA_ENABLE” on
page 14
).
ATA data bit 8
.
ATA data bit 9
.
ATA data bit 10
.
ATA data bit 11
.
Ground
.
V
CC
. Connect to 3.3V power source.
No connect
.
Input
VBUS_ATA_ENABLE
(
ATA_EN
)
DD8
DD9
DD10
DD11
GND
V
CC
NC
Input
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
45
46
47
48
N/A
N/A
N/A
52
53
54
55
N/A
N/A
N/A
IO
[1]
IO
[1]
IO
[1]
IO
[1]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PWR
NC
36
[3]
13
[3]
54
[3]
N/A
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GND
DD12
DD13
DD14
DD15
GND
IO
[3]
General purpose IO pins
(See
“GPIO Pins” on
page 13
). The GPIO pins must be tied to GND if
functionality is not used.
N/A
49
50
51
52
53
N/A
56
1
2
3
4
GND
IO
[1]
IO
[1]
IO
[1]
IO
[1]
GND
Ground
.
ATA data bit 12
.
ATA data bit 13
.
ATA data bit 14
.
ATA data bit 15
.
Ground
.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
(continued)
100
TQFP
56
QFN
56
SSOP
Pin Name
Pin
Type
Default State
at Startup
Pin Description
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CY7C68300C-56LFXC 功能描述:USB 接口集成電路 USB Hi Spd Peripherals RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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