參數(shù)資料
型號(hào): CY7C68300C
廠商: Cypress Semiconductor Corp.
英文描述: EZ-USB AT2LP USB 2.0 to ATA/ATAPI Bridge(EZ-USB AT2LP USB 2.0到ATA/ATAPI橋接器)
中文描述: 的EZ - USB AT2LP產(chǎn)品的USB 2.0的ATA / ATAPI橋(的EZ - USB AT2LP產(chǎn)品的USB 2.0到ATA / ATAPI接口橋接器)
文件頁(yè)數(shù): 8/42頁(yè)
文件大?。?/td> 761K
代理商: CY7C68300C
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A
Page 8 of 42
Pin Descriptions
The following table lists the pinouts for the 56-pin SSOP, 56-pin
QFN and 100-pin TQFP package options for the AT2LP. Refer
to the
“Pin Diagrams” on page 3
for differences between the
68300C/01C and 68320C/321C pinouts for the 56-pin
packages. For information on the CY7C68300A pinout, refer
to the CY7C68300A data sheet that is found in the ’EZ-USB
AT2’ folder of the
CY4615C reference design kit CD
.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
100
TQFP
1
2
3
4
5
6
7
8
9
56
QFN
55
56
1
2
N/A
56
SSOP
6
7
8
9
N/A
Pin Name
Pin
Type
PWR
GND
I
[1]
I
[1]
Default State
at Startup
Pin Description
V
CC
GND
IORDY
DMARQ
GND
V
CC
. Connect to 3.3V power source.
Ground
.
ATA control
. Apply a 1k pull up to 3.3V.
ATA control
.
Ground
.
Input
Input
3
10
AV
CC
PWR
Analog V
CC
. Connect to V
CC
through the shortest path
possible.
24 MHz crystal output.
(See
“XTALIN, XTALOUT” on
page 11
).
24 MHz crystal input.
(See
“XTALIN, XTALOUT” on
page 11
).
Analog ground
. Connect to ground with as short a
path as possible.
No connect
.
10
4
11
XTALOUT
Xtal
Xtal
11
5
12
XTALIN
Xtal
Xtal
12
6
13
AGND
GND
13
14
15
16
17
18
19
20
21
22
N/A
N/A
NC
7
8
9
10
11
12
N/A
14
15
16
17
18
19
N/A
V
CC
DPLUS
DMINUS
GND
V
CC
GND
SYSIRQ
PWR
IO
IO
GND
PWR
GND
I
V
CC
. Connect to 3.3V power source.
USB D+ signal
(See
“DPLUS, DMINUS” on page 11
).
USB D–signal
(See
“DPLUS, DMINUS” on page 11
).
Ground
.
V
CC
. Connect to 3.3V power source.
Ground
.
USB interrupt request.
(See
“SYSIRQ” on page 12
).
Active HIGH. Connect to GND if functionality is not
used.
Ground
.
Hi-Z
Hi-Z
Input
23
24
25
26
[3]
N/A
N/A
GND
GND
13
[3]
20
PWR500#
[2]
(
PU 10K
)
O
bMaxPower request granted indicator.
(See
“PWR500#” on page 14
). Active LOW.
N/A for
CY7C68320C/CY7C68321C 56-pin packages.
Reserved
. Tie to GND.
No connect
.
Clock signal for I
2
C interface.
(See
“SCL, SDA” on
page 11
). Apply a 2.2k pull up resistor.
27
28
29
14
N/A
15
21
N/A
22
GND (
RESERVED
)
NC
SCL
O
Active for
several ms at
startup.
Notes
1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See
“VBUS_ATA_ENABLE” on
.
2. A ‘#’ sign after the pin name indicates that it is active LOW.
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