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| 型號(hào)： | CY8C22113-24PI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 196/304頁(yè) |
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| 代理商： | CY8C22113-24PI |
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17. Digital Blocks
CY8C22xxx Preliminary Data Sheet
196
Document No. 38-12009 Rev. *D
December 22, 2003
17.1.10
SPI Master Function
The SPI Master (SPIM) offers SPI operating modes 0-3. By
default, the MSB of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSB first.
When configured for SPIM, DR0 functions as a shift register,
with input from the DATA input (MISO) and output to the pri-
mary output F1 (MOSI). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle,
before it is clocked into the shift register.
The SPIM controls data transmission between master and
slave because it generates the bit clock for internal clocking
and for clocking the SPIS. The bit clock is derived from the
CLK input selection. Since the PSoC system clock genera-
tors produce clocks with varying duty cycles, the SPIM
divides the input CLK by two to produce a bit clock with a
fifty percent duty cycle. This clock is gated, to provide the
SCLK output on the auxiliary output, during byte transmis-
sions.
There are four control bits and four status bits in the Control
register that provide for host interfacing and synchroniza-
tion.
The SPIM hardware has no support for driving the Slave
Select (SS_) signal. The behavior and use of this signal is
application and chip dependent and, if required, must be
implemented in firmware.
This SPIM function may not be chained.
17.1.10.1
Block Interrupt
The SPIM block has a selection of two interrupt sources:
Interrupt on TX Reg Empty (default), or interrupt on SPI
Complete. Mode bit 1 in the Function register controls the
selection.
If SPI Complete is selected as the block interrupt, the Con-
trol register must be read in the interrupt routine so that this
status bit is cleared; otherwise, no subsequent interrupts are
generated.
17.1.11
SPI Slave Function
The SPI Slave (SPIS) offers SPI operating modes 0-3. By
default, the MSB of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSB first.
When configured for SPI, DR0 functions as a shift register,
with input from the DATA input (MOSI) and output to the pri-
mary output F1 (MISO). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle
before it is clocked into the shift register.
The SPIS function derives all clocking from the SCLK input
(typically an external SPI Master). This means that the mas-
ter must initiate all transmissions. For example, to read a
byte from the SPIS, the master must send a byte.
Since there are no internal clocks used in the SPIS, it may
be clocked asynchronously (if input synchronization is
turned off). In this case, synchronization between the CPU
and the SPIS block can be accomplished with polling and/or
interrupts.
There are four control bits and four status bits in the Control
register that provide for host interfacing and synchroniza-
tion.
In the SPIS, there is an additional data input, Slave Select
(SS_), which is an active low signal. SS_ must be asserted
to enable the SPIS to receive and transmit. SS_ has two
high-level functions: 1) To allow for the selection of a given
slave in multi-slave environment, and 2) To provide addi-
tional clocking for TX data queuing in SPI modes 0 and 1.
SS_ may be controlled from an external pin, through a Row
Input.
When SS_ is negated, the SPIS ignores any MOSI/SCLK
input from the master. In addition, the SPIS state machine is
reset, and the MISO output is forced to idle at logic '1'. This
allows for a wired-AND connection in a multi-slave environ-
ment. Note that if Hi-Z output is required when the slave is
not selected, this behavior must be implemented in firmware
with IO writes to the port drive register.
17.1.11.1
Usability Exceptions
The following are usability exceptions for the SPI Slave
function.
1.
The SS_ input must be synchronized, but the MOSI and
SCLK inputs may be synchronized or not. Unsynchro-
nized data and clock inputs reduce the latency through
the block and thus allow an SPI system to run at a
slightly higher clock rate.
17.1.11.2
Block Interrupt
The SPIS block has a selection of two interrupt sources:
Interrupt on TX Reg Empty (default) or interrupt on SPI
Complete (same selection as the SPIM). Mode bit 1 in the
Function register controls the selection.
If SPI Complete is selected as the block interrupt, the Con-
trol register must still be read in the interrupt routine so that
this status bit is cleared; otherwise, no subsequent inter-
rupts are generated.
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