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參數資料
| 型號： | CY8C22113 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | PSoC混合信號陣列 |
| 文件頁數： | 269/304頁 |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22113 |
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December 22, 2003
Document No. 38-12009 Rev. *D
269
CY8C22xxx Preliminary Data Sheet
26. I2C
Bit 0: Byte Complete.
The I2C hardware operates on a
byte basis. In Transmit mode, this bit is set and an interrupt
is generated at the end of nine bits (the transmitted byte +
the received ACK). In Receive mode, the bit is set after the
eight bits of data have been received. When this bit is set,
an interrupt is generated at these data sampling points,
which are associated with the SCL input clock rising (see
details in the Timing section). If the host responds with a
write back to this register before the subsequent falling edge
of SCL (which is approximately one-half bit time), the trans-
fer will continue without interruption. However, if the host is
unable to respond within that time, the hardware will hold
the SCL line low, stalling the I2C bus. In both Master and
Slave mode, a subsequent write to the I2C_SCR register
will release the stall.
For additional information, reference the
I2C_SCR register
on page 126
.
26.3.3
I2C_DR Register
This register is the I2C data register and provides read/write
access to the shift register. It is not buffered and therefore,
writes and valid data reads may only occur at specific points
in the transfer. These cases are outlined as follows.
I
Master or Slave Receiver
Data in the I2C_DR register
is only valid for reading, when the Byte Complete status
bit is set. Data bytes must be read from the register
before writing to the I2C_SCR register, which continues
the transfer.
I
Master Start or Restart
Address bytes must be written
in I2C_DR before the Start or Restart bit is set in the
I2C_MSCR register, which causes the Start or Restart to
be generated and the address shifted out.
I
Master or Slave Transmitter
Data bytes must be writ-
ten to the I2C_DR register before the transmit bit is set in
the I2C_SCR register, which causes the transfer to con-
tinue.
For additional information, reference the
I2C_DR register on
page 127
.
26.3.4
I2C_MSCR Register
This register is the I2C master status and control register.
Bits 7 to 4: Reserved.
Bit 3: Bus Busy.
This read only bit is set to ‘1’ by any Start
condition and reset to ‘0’ by a Stop condition. It may be
polled by firmware to determine when a bus transfer may be
initiated.
Bit 2: Master Mode.
This bit indicates that the device is
operating as a Master. It is set in the detection of this block’s
Start condition and reset in the detection of the subsequent
Stop condition.
Bit 1: Restart Gen.
This bit is only used at the end of a
Master transfer (as noted in Other Cases 1 and 2 above of
the Start Gen bit). If an address is loaded into the data regis-
ter and this bit is set prior to NACKing (Master receiver) or
resetting the transmit bit (Master transmitter), or after a Mas-
ter transmitter is NACKed by the Slave, a Restart condition
will be generated, followed by the transmission of the
address byte.
Bit 0: Start Gen.
Before setting this bit, firmware must write
the address byte to send into the I2C_DR register. When
this bit is set, the Start condition is generated, followed
immediately by the transmission of the address byte. (No
control in the I2C_SCR register is needed for the Master to
initiate a transmission; the direction is inherently “transmit”.)
The bit is automatically reset to ‘0’ after the Start has been
generated.
There are three possible outcomes as a result of setting the
Start Gen bit:
1.
The bus is free and the Start condition is generated suc-
cessfully. A Byte Complete interrupt will be generated
after the Start and the address byte has been transmit-
ted. If the address was ACKed by the receiver, the firm-
ware may then proceed to send data bytes.
2.
The Start command is too late. Another Master in a
Multi-Master environment has generated a valid Start
and the bus is busy. The resulting behavior depends
upon whether Slave mode is enabled.
Slave mode is enabled: A Start and address byte inter-
rupt will be generated. When reading the I2C_MSCR,
the Master will see the Start Gen bit still set and the
I2C_SCR will have the Address bit set, indicating that
the block has been addressed as a Slave.
Table 26-6. I2C_MSCR Master Status and Control
Register
Bit
0
Access
R/W
Description
Mode
Master
Only
Start Gen
1 = Generate a Start condition and send a
byte (address) to the I2C bus.
This bit is cleared by hardware when the
Start generation is complete.
Restart Gen
1 = Generate a Restart condition.
This bit is cleared by hardware when the
Start generation is complete.
1
R/W
Master
Only
2
RO
Master Mode
This bit is set to ‘1’ when a start condition,
generated by this block, is detected and
reset to ‘0’ when a stop condition is
detected.
Bus Busy
This bit is set to ‘1’ when any Start condition
is detected, and reset to ‘0’ when a Stop
condition is detected.
Master
Only
3
RO
Master
Only
Table 26-6. I2C_MSCR Master Status and Control
Register
(continued)
Bit
Access
Description
Mode
相關PDF資料 |
PDF描述 |
|---|---|
| CY8C22113-24PI | PSoC Mixed Signal Array |
| CY8C22113-24SI | PSoC Mixed Signal Array |
| CY8C22213 | PSoC Mixed Signal Array |
| CY8C22213-24LFI | PSoC Mixed Signal Array |
| CY8C22213-24PI | PSoC Mixed Signal Array |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY8C22113_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
| CY8C22113-24PI | 功能描述:IC MCU 2K FLASH 256B 8-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設備:欠壓檢測/復位，DMA，LCD，POR，PWM，WDT 輸入/輸出數:76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SI | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設備:欠壓檢測/復位，DMA，LCD，POR，PWM，WDT 輸入/輸出數:76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SIT | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設備:欠壓檢測/復位，DMA，LCD，POR，PWM，WDT 輸入/輸出數:76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
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