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| 型號(hào)： | CY8C22213-24LFI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, QCC32 |
| 封裝： | 5 X 5 MM, MLF-32 |
| 文件頁(yè)數(shù)： | 79/304頁(yè) |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22213-24LFI |
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December 22, 2003
Document No. 38-12009 Rev. *D
79
CY8C22xxx Preliminary Data Sheet
12. Sleep and Watchdog
12.4.3
Bandgap Refresh
During normal operation, the bandgap circuit provides a
voltage reference (VREF) to the system, for use in the ana-
log blocks, Flash, and low voltage detect (LVD) circuitry.
Normally, the bandgap output is connected directly to the
VREF signal. However, during sleep, the bandgap reference
generator block and LVD circuits are completely powered
down. The bandgap and LVD blocks are periodically re-
enabled during sleep in order to monitor for low voltage con-
ditions.
This is accomplished by turning on the bandgap periodically,
allowing it time to start up for a full 32K clock period and
connecting it to VREF to refresh the reference voltage for
the following 32K clock period as shown in
Figure 12-3
.
During the second 32K clock period of the refresh cycle, the
LVD circuit is allowed to settle during the high time of the
32K clock. During the low period of the second 32K clock,
the LVD interrupt is allowed to occur.
Figure 12-3. Bandgap Refresh Operation
The rate at which the refresh occurs is related to the 32 kHz
clock and controlled by the Power System Sleep Duty Cycle
(PDDSC, bits [7:6] of the ECO_TR register).
Table 12-4
enu-
merates the available selections. The default setting (128
sleep timer counts) is applicable for many applications, giv-
ing a typical average device current under 5
μ
A.
12.4.4
Watchdog Timer (WDT)
On device boot up, the WDT is initially disabled. The PORS
bit in the System Control register controls the enabling of the
WDT. On boot, the PORS bit is initially set to '1', indicating
that either a POR or XRES event has occurred. The WDT is
enabled by clearing the PORS bit. Once this bit is cleared
and the Watchdog timer is enabled, it cannot be subse-
quently disabled (the PORS bit cannot be set to '1' in firm-
ware, it can only be cleared). The only way to disable the
Watchdog function, after it is enabled, is through a subse-
quent POR or XRES. Although the WDT is disabled during
the first time through initialization code after a POR or
XRES, all code should be written as if it is enabled (i.e., the
WDT should be cleared periodically). This is because, in the
initialization code after a WDR event, the Watchdog Timer is
enabled, so all code must be cognizant of this.
The Watchdog timer is three counts of the Sleep Timer inter-
rupt output and therefore, the watchdog interval is three
times the selected Sleep Timer interval. The available selec-
tions for the Watchdog interval are shown in
Table 12-2
.
When the Sleep Timer interrupt is asserted, the watchdog
timer increments. When the counter reaches three, a termi-
nal count is asserted. This terminal count is registered by
the 32 kHz clock. Therefore, the WDR (Watchdog Reset)
signal will go high after the following edge of the 32 kHz
clock and be held asserted for 1 cycle (30us nominal). The
flip-flop that registers the WDT terminal count is not reset by
the WDR signal when it is asserted, but is reset by all other
resets. This timing is shown in
Figure 12-4
.
Figure 12-4. Watchdog Reset
Once enabled, the WDT must be periodically cleared in firm-
ware. This is accomplished with a write to the RES_WDT
register. This write is data independent, so any write will
clear the Watchdog timer. (Note: A write of 38h will also
clear the Sleep timer). If for any reason the firmware fails to
clear the WDT within the selected interval, the circuit will
assert WDR to the device. WDR is equivalent in effect to
any other reset. All internal registers are set to their reset
state. An important aspect to remember about WDT resets
is that RAM initialization can be disabled (IRAMDIS in
CPU_SCR1). In this case, the SRAM contents are unaf-
fected, so that when a WDR occurs, program variables are
persistent through this reset.
In practical application, it is important to know that the
Watchdog Timer interval can be anywhere between two and
three times the Sleep Timer interval. The only way to guar-
antee that the WDT interval is a full 3X of the Sleep interval
is to clear the Sleep timer (write 38h) when clearing the
WDT register. However, this is not possible in applications
Table 12-4. Power System Sleep Duty Cycle Selections
PSSDC
00b (default)
01b
10b
11b
Sleep Timer Counts
256
1024
64
16
Period (Nominal)
8 ms
31.2 ms
2 ms
500 us
CLK32K
Band Gap
VREF
Bandgap is turned on,
but not yet connected
to VREF.
VREF is slowly
leaking to ground.
Bandgap output is
connected to VREF.
Voltage is refreshed.
Bandgap is powered
down until next
refresh cycle.
Low voltage monitors are
active during CLK32 low.
SLEEP INT
WD RESET
(WDR)
CLK32K
2
WD COUNT
3
0
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