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Contents
CY8C22xxx Preliminary Data Sheet
4
Document No. 38-12009 Rev. *D
December 22, 2003
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
Source Direct.................................................................................................40
Source Indexed..............................................................................................40
Destination Direct...........................................................................................40
Destination Indexed.......................................................................................41
Destination Direct Source Immediate ............................................................41
Destination Indexed Source Immediate.........................................................41
Destination Direct Source Direct....................................................................42
Source Indirect Post Increment......................................................................42
Destination Indirect Post Increment...............................................................42
Register Definitions..............................................................................................................43
3.6.1
CPU_F (Flag) Register ..................................................................................43
3.6
4. Supervisory ROM (SROM)
......................................................................................45
4.1
Architectural Description......................................................................................................45
4.1.1
Additional SROM Feature..............................................................................46
4.1.2
SROM Function Descriptions.........................................................................46
4.2
Register Definitions..............................................................................................................49
4.2.1
CPU_SCR1 Register .....................................................................................49
4.3
Clocking...............................................................................................................................49
5. Interrupt Controller
.................................................................................................51
5.1
Architectural Description......................................................................................................52
5.2
Register Definitions..............................................................................................................53
5.2.1
INT_CLRx Register........................................................................................53
5.2.2
INT_MSKx Register.......................................................................................53
5.2.3
INT_VC Register............................................................................................53
5.2.4
CPU_F Register.............................................................................................53
6. General Purpose IO (GPIO)
....................................................................................55
6.1
Architectural Description......................................................................................................55
6.1.1
Digital IO........................................................................................................55
6.1.2
Global IO........................................................................................................55
6.1.3
Analog IO.......................................................................................................56
6.1.4
GPIO Block Interrupts....................................................................................56
6.2
Register Definitions..............................................................................................................58
6.2.1
PRTxDR Registers.........................................................................................58
6.2.2
PRTxIE Registers ..........................................................................................58
6.2.3
PRTxGS Registers.........................................................................................58
6.2.4
PRTxDMx Registers ......................................................................................58
6.2.5
PRTxICx Registers ........................................................................................59
7. Analog Output Drivers
............................................................................................61
7.1
Architectural Description......................................................................................................61
7.2
Register Definitions..............................................................................................................61
7.2.1
ABF_CR0 Register ........................................................................................61
8. Internal Main Oscillator (IMO)
.................................................................................63
8.1
Architectural Description......................................................................................................63
8.2
Register Definitions..............................................................................................................63
8.2.1
IMO_TR Register...........................................................................................63