參數(shù)資料
型號(hào)： CY8C22213-24SIT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO20
封裝： 0.300 INCH, MO-119, SOIC-20
文件頁(yè)數(shù)： 190/304頁(yè)
文件大?。?/td> 2956K
代理商： CY8C22213-24SIT
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17. Digital Blocks
CY8C22xxx Preliminary Data Sheet
190
Document No. 38-12009 Rev. *D
December 22, 2003
Note 1
If the input data source for a given block comes from
another block, the destination block must be enabled prior to
the source block being enabled.
17.1.2
Input Clock Resynchronization
Digital blocks allow a clock selection from one of 16
sources. Possible sources are the system clocks (VC1,
VC2, VC3, SYSCLK, and SYSCLKX2), pin inputs, and other
digital block outputs. To manage clock skew and ensure that
the interfaces between blocks meet timing in all cases, all
digital block input clocks must be resynchronized to either
SYSCLK or SYSCLKX2, which are the source clocks for all
chip clocking. Also, SYSCLK or SYSCLKX2 may be used
directly. The AUXCLK bits in the DxBxxOU register are used
to specify the input synchronization. The following rules
apply to the use of input clock resynchronization.
1.
If the clock input is derived (e.g., divided down) from
SYSCLK, re-synchronize to SYSCLK at the digital block.
Most chip clocks are in this category. For example, VC1
and VC2, and the output of other blocks clocked by VC1
and VC2 or SYSCLK (setting 01 in AUXCLK).
2.
If the clock input is derived from SYSCLKX2, re-synchro-
nize to SYSCLKX2. For example, VC3 clocked by
SYSCLKX2, or other digital blocks clocked by
SYSCLKX2 (setting 10 in AUXCLK).
3.
Choose direct SYSCLK (setting 11 in AUXCLK).
4.
Choose direct SYSCLKX2 (select SYSCLKX2 in the
Clock Input field of the DxBxxIN register).
5.
Bypass synchronization. This should be a very rare
selection. Because if clocks are not synchronized, they
may fail setup to CPU read and write commands. How-
ever, it is possible for an external pin to asynchronously
clock a digital block. For example, if the user is willing to
synchronize CPU interaction through interrupts or other
techniques (setting 00 in AUXCLK).
The following notes enumerate configurations that are not
allowed, although the hardware does not prevent them. The
summary of these notes is that the clock dividers (VC1,
VC2, and VC3) may not be configured in such a way as to
create an output clock that is equal to SYSCLK or
SYSCLKX2.
Note 1
When VC1 is configured to divide by one, choosing
an input clock of VC1 is not allowed. This configuration pro-
duces a clock frequency that is equal to SYSCLK; therefore,
SYSCLK direct should be used by setting the AUXCLK bits
in DxBxOU to 11b.
Note 2
When both VC2 and VC1 are configured to divide
by one, choosing an input clock of VC2 is not allowed. This
configuration produces a clock frequency that is equal to
SYSCLK; therefore, SYSCLK direct should be used by set-
ting the AUXCLK bits in DxBxOU to 11b.
Note 3
When VC3 is configured to divide by one with a
source clock of SYSCLK, choosing an input clock of VC3 is
not allowed. This configuration produces a clock frequency
that is equal to SYSCLK. There are two other VC3 configu-
rations to avoid that will result in an output frequency equal
to SYSCLK. The first is when VC3 is configured to divide by
one with a source clock of VC1 divide by one. The second is
when VC3 is configured to divide by one with a source clock
of VC2 divide by one and VC1 is also configured to divide by
one. All of these configurations result in a VC3 frequency
equal to SYSCLK and this is not allowed. When a frequency
equal to SYSCLK is desired, SYSCLK direct should be used
by setting the AUXCLK bits in DxBxOU to 11b.
Note 4
When VC3 is configured to divide by one with a
source clock of SYSCLKX2, choosing an input clock of VC3
is not allowed. This configuration produces a clock fre-
quency that is equal to SYSCLKX2. When a frequency
equal to SYSCLKX2 is desired, SYSCLKX2 should be
selected by setting the Clock Input bits of the DxBxxIN regis-
ter to 4h and the AUXCLK bits of DxBxOU to 00b.
All of these issues have been addressed in the actual clock
resynchronizer, illustrated in
Figure 17-1
.
Figure 17-1. Input Clock Resynchronization
16-1
CLK MUX
4-1
AUXCLK
MUX
SYSCLK
SYSCLK2
BLK CLK
2-1
SEL_SYSCLK2
0
1
SYSCLK
00 = BYPASS
01 = SYSCLK
10 = SYSCLK2
11 = SYSCLK DIRECT
SYSCLK2
Current Decoding
Table 17-2: AUXCLK Bit Selections
Code
00
01
Description
Bypass
Resync to
SYSCLK
(24 MHz)
Resync to
SYSCLK2
(48 MHz)
SYSCLK Direct Use this setting to clock the block directly using SYSCLK. Note that this setting is not strictly related to clock resynchronization,
but since SYSCLK cannot resync itself, it allows a direct skew controlled SYSCLK source.
Usage
Use this setting only for asynchronous inputs. Also used when SYSCLK2 (48 MHz) is selected.
Use this setting for any SYSCLK based clock. VC1, VC2, VC3 driven by SYSCLK, digital blocks with SYSCLK based source
clocks, broadcast bus with source based on SYSCLK, row input and row outputs with source based on SYSCLK.
10
Use this setting for any SYSCLK2 based clock. VC3 driven by SYSCLK2, digital blocks with SYSCLK2 based source clocks,
broadcast bus with source based on SYSCLK2, row input and row outputs with source based on SYSCLK2.
11
相關(guān)PDF資料
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CY8C24794-SPAX PSoCTM Mixed-Signal Array
CY8C24794-SPE PSoCTM Mixed-Signal Array
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