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參數(shù)資料
| 型號(hào)： | CY9C62256-70ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | 32K x 8 Magnetic Nonvolatile CMOS RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO28 |
| 封裝： | 8 X 13.40 MM, TSOP-28 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | CY9C62256-70ZC |
PRELIMINARY
CY9C62256
Document #: 38-15001 Rev. *E
Page 5 of 11
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
CY9C62256-70
Min.
Unit
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10,11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
10.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write pulse width for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[8,9]
CE LOW to Low Z
[8]
CE HIGH to High Z
[8,9]
CE LOW to Power-up
CE HIGH to Power-down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
5
70
35
5
25
5
25
0
70
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[8, 9]
WE HIGH to Low Z
[8]
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
3.0V
5V
OUTPUT
R1 1800
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
5V
OUTPUT
R1 1800
R2
990
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.77V
Equivalent to:
THEVENIN EQUIVALENT
639
ALL INPUT PULSES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY9C62256-70ZI | 32K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264 | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70SNI | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70PI | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70SI | 8K x 8 Magnetic Nonvolatile CMOS RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY9C62256-70ZI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:32K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70PC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70PI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70SC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
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