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參數(shù)資料
| 型號： | CYDC128B16-55AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| 中文描述： | 8K X 16 DUAL-PORT SRAM, 55 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 580K |
| 代理商： | CYDC128B16-55AXI |
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E
Page 8 of 26
Table 3. Input Read Register Operation
[16, 19]
SFEN
CE
R/W
OE
UB
LB
ADDR
x0000-Max VALID
[17]
VALID
[17]
Standard Memory Access
VALID
[18]
X
I/O
0
–
I/O
1
I/O
2
–
I/O
15
Mode
H
L
H
L
L
L
L
L
H
L
X
L
x0000
IRR Read
Table 4. Output Drive Register
[20]
SFEN
CE
R/W
OE
X
[21]
UB
L
[17]
LB
L
[17]
ADDR
x0000-Max VALID
[17]
I/O
0
–
I/O
4
I/O
5
–
I/O
15
VALID
[17]
Standard Memory Access
ODR Write
[20, 22]
ODR Read
[20]
Mode
H
L
H
L
L
L
X
X
L
x0001
VALID
[18]
VALID
[18]
X
L
L
H
L
X
L
x0001
X
Table 5. Semaphore Operation Example
Function
I/O
0
–
I/O
15
Left
1
0
0
1
1
0
1
1
1
0
1
I/O
0
–
I/O
15
Right
1
1
1
0
0
1
1
0
1
1
1
Status
No action
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
Semaphore-free
Left Port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore-free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore-free
Notes:
16.SFEN = V
for IRR reads.
17.UB or LB = V
. If LB = V
IL
, then DQ<7:0> are valid. If UB = V
IL
then DQ<15:8> are valid.
18.LB must be active (LB = V
) for these bits to be valid.
19.SFEN active when either CE
= V
or CE
R
= V
IL
. It is inactive when CE
L
= CE
R
= V
IH
.
20.SFEN = V
for ODR reads and writes.
21.Output enable must be low (OE = V
) during reads for valid data to be output.
22.During ODR writes data will also be written to the memory.
[+] Feedback
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| CYDC256B16-55AXI | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYDC256B16 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
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| CYDC256B16-55AXC | 制造商:Cypress Semiconductor 功能描述: |
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| CYDC61061012-48BAI | 制造商:Cypress Semiconductor 功能描述: |
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