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參數(shù)資料
| 型號： | CYDM064B16 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1.8V 4K/8K/16K x 16 MoBL㈢ Dual-Port Static RAM |
| 中文描述： | 1.8 4K/8K/16K㈢× 16的MoBL雙端口靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 583K |
| 代理商： | CYDM064B16 |
CYDM256B16
CYDM128B16
CYDM064B16
Document #: 001-00217 Rev. *E
Page 4 of 25
Functional Description
The CYDM256B16, CYDM128B16, CYDM064B16 are
low-power CMOS 4K, 8K,16K x 16 dual-port static RAMs.
Arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 16-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 32-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 32-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications
status
video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
buffering,
and
dual-port
The CYDM256B16, CYDM128B16, CYDM064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
packages.
Power Supply
The core voltage (V
CC
) can be 1.8V, 2.5V or 3.0V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the V
DDIOL
and V
DDIOR
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
Table 1
.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user wishes to access a semaphore flag,
Pin Definitions
Left Port
Right Port
Description
CE
L
R/W
L
OE
L
A
0L
–A
13L
I/O
0L
–I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
–A
13R
I/O
0R
–I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
IRR0, IRR1
Chip Enable
Read/Write Enable
Output Enable
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices)
.
Data Bus Input/Output for x16 devices
Semaphore Enable
Upper Byte Select (I/O
8
–I/O
15
)
.
Lower Byte Select (I/O
0
–I/O
7
)
.
Interrupt Flag
Busy Flag
Input Read Register for CYDM064B16, CYDM128B16.
A13L, A13R for CYDM256B16.
ODR0-ODR4
Output Drive Register; These outputs are Open Drain.
SFEN
Special Function Enable
M/S
Master or Slave Select
V
CC
GND
Core Power
Ground
V
DDIOL
V
DDIOR
NC
Left Port I/O Voltage
Right Port I/O Voltage
No Connect
.
Leave this pin Unconnected.
[+] Feedback
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYDM064B16_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL? Dual-Port Static RAM |
| CYDM064B16_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL Dual-Port Static RAM |
| CYDM064B16_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 MoBL? Dual-Port Static RAM |
| CYDM064B16-40BVXI | 功能描述:靜態(tài)隨機存取存儲器 64K 4Kx16 MoBL Dual Port IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDM064B16-40BVXIT | 功能描述:IC SRAM 64KBIT 40NS 100VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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