參數(shù)資料
型號: CYDM128B16
廠商: Cypress Semiconductor Corp.
英文描述: 1.8V 4K/8K/16K x 16 MoBL㈢ Dual-Port Static RAM
中文描述: 1.8 4K/8K/16K㈢× 16的MoBL雙端口靜態(tài)存儲器
文件頁數(shù): 18/25頁
文件大?。?/td> 583K
代理商: CYDM128B16
CYDM256B16
CYDM128B16
CYDM064B16
Document #: 001-00217 Rev. *E
Page 18 of 25
Write Cycle No.1: R/W Controlled Timing
[37, 38, 39, 40, 41, 42]
Write Cycle No. 2: CE Controlled Timing
[37, 38, 39, 44]
Notes:
39.t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
40.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t
) to allow the I/O drivers to turn off and data to
be placed on the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
.
41.To access RAM, CE = V
, SEM = V
.
42.To access upper byte, CE = V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE = V
, LB = V
, SEM = V
.
43.Transition is measured
±
0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
44.During this period, the I/O pins are in the output state, and input signals must not be applied.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
[43]
[43]
[40]
[41, 42]
NOTE 44
NOTE 44
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
[41, 42]
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