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| 型號： | CYII4SM1300AA-QBC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1.3 MPxl Rolling Shutter CMOS Image Sensor |
| 中文描述： | 1.3 MPxl卷簾門的CMOS圖像傳感器 |
| 文件頁數(shù)： | 14/37頁 |
| 文件大小： | 1168K |
| 代理商： | CYII4SM1300AA-QBC |
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IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 14 of 37
Table 4. Pins involved in output amplifier circuitry
Name
No.
Function
Analog signals
Extin
12
External input of the output amplifier
Active if Sel_extin = 1
Output
13
Analog output signal
To be connected to the input of the ADC (in_adc, pin 73)
Digital Controls
Sel_extin
9
1 = external input pin (extin) is applied at the input of the amplifier
0 = output amplifier is connected to the image sensor array
gc_bit0
17
LSB
Control bits for output amplifier gain setting
Gain adjustment between 1.2 (0000) & 16X (1111)
MSB
gc_bit1
18
gc_bit2
19
gc_bit3
20
unitygain
21
1 = output amplifier in unity feedback mode
0 = output amplifier gain controlled by gc_bit0...3
calib_s
16
Slow (or incremental) output offset level adjustment (calibration of output
amplifier). Offset adjustment converges after about 100 pulses on calib_s
Amplifier input should refer to a 'zero signal' at the moment of the 1->0
transition on calib_s
0 = connect to capacitor (of stage 2) and in- (of stage 1)
1 = connect to DAC output (of stage 2) and out (of stage1)
calib_f
22
Fast (=in 1 cycle) output offset level adjustment (calibration of output
amplifier)
Offset level is adjusted when both calib_f and unitygain are high
Amplifier input should refer to 'zero signal' when calib_f is high
1 = connect DAC output to offset of capacitor
0 = DAC output disconnected
dac_b0
26
LSB
Control bits for output offset level adjustment
Between Vlow_dac (0000) & Vhigh_dac (1111)
MSB
dac_b1
25
dac_b2
24
dac_b3
23
Reference voltages
Vlow_dac
14
Low and high references for offset control DAC of the analog output.
The range of this resistive division DAC should be about 1V to 2.5V. If the
range is not OK, one will notice that it is not possible to adjust the output
voltage to the appropriate level of the ADC. As the internal division resistor is
about 1.3 Kohm, we suggest to tie Vlow_dac with 1K to GND and Vhigh_dac
with 2K7 to VDD.
Vhigh_dac
15
Nbias_oamp
27
Output amplifier speed/power.
Connect with 100 K to VDD and decouple with 100 nF to GND. This setting
yields 10 MHz nominal pixel rate. Lowering the resistance does increasing
this rate.
Clip
83
Voltage that can be used to clip the output signal
Clips output if output signal > 'Vclip - Vth, PMOS' with Vth,PMOS=-1V
Default: 5 V (no clipping)
[+] Feedback
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