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參數(shù)資料
| 型號： | CYII4SM1300AA-QBC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1.3 MPxl Rolling Shutter CMOS Image Sensor |
| 中文描述： | 1.3 MPxl卷簾門的CMOS圖像傳感器 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大小： | 1168K |
| 代理商： | CYII4SM1300AA-QBC |
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IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 18 of 37
ADC timing
The ADC converts on the falling edge of the CLK_ADC clock.
The input signal should be stable during a time Ts before the
falling clock edge. The digital output is available Td after the
falling clock edge (Figure 13., Ts = 100 ns, Td = 50 ns). These
values are the delays to obtain a stable LSB after a half-scale
swing of the input signal. For the MSB to become stable, Ts=20
ns is sufficient. For a full scale input swing (which normally
doesn't appear with image sensors), Ts is 140 ns for the LSB
and 20 ns for the MSB.
Figure 13. ADC timing
TRI_ADC can be used to put the output bits in a tristate mode
(e.g. for bi-directional busses). If this is used, the output signal
becomes valid 50 ns after the falling edge on TRI_ADC.
BITINVERT can be used to invert the output word, if necessary
(one's complement).
When NONLINEAR is high, the ADC conversion is non-linear.
The contrast will be higher in dark image regions, and lower in
bright areas, similar to gamma correction.
Ts
Td
100 ns
CLK_ADC
IN_ADC
D0…D9
Table 7. pins of the ADC
Name
No.
Description
Analog signals
IN_ADC
73
Input, connect to sensor's output (pin 13)
Input range is between 2 & 4 V (VLOW_ADC & VHIGH_ADC)
Digital Controls
CLK_ADC
62
ADC Clock
ADC converts on falling edge
TRI_ADC
63
Tristate control of ADC digital outputs
1 = tristate; 0 = output
NONLINEAR
67
1 = non-linear analog-digital conversion
0 = linear analog-digital conversion
BITINVERT
39
1 = invert output bits
0 = no inversion of output bits
Digital output
DO… D9
51…42
Output bits
D0 = LSB, D9 = MSB
Reference voltages
[+] Feedback
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| CYII4SM1300AA-QDC | 制造商:Cypress Semiconductor 功能描述:CYII4SM1300AA-QDC |
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