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參數(shù)資料
| 型號： | CYII4SM1300AA-QDC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 圖像傳感器 |
| 英文描述： | 1.3 MPxl Rolling Shutter CMOS Image Sensor |
| 中文描述： | IMAGE SENSOR-CMOS, 1280(H) X 1024(V) PIXEL, 23fps, SQUARE, SURFACE MOUNT |
| 封裝： | 0.71 MM HEIGHT, 0.04 INCH PITCH, CERAMIC, LCC-84 |
| 文件頁數(shù)： | 10/37頁 |
| 文件大小： | 1168K |
| 代理商： | CYII4SM1300AA-QDC |
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IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 10 of 37
Figure 5. shows the pixel response curve in linear response
mode. This curve is the relation between the electrons
detected in the pixel and the output signal. This curve was
measured with light of 600 nm, with an integration time of
138.75 ms (10 MHz pixel rate), at minimal gain setting 0000.
The resulting voltage/electron curve is independent of these
parameters. The conversion gain is 18 uV/electron for this gain
setting.
Note that the upper part of the curve (near saturation) is
actually a logarithmic response, similar to the FUGA1000
sensor. The level of saturation can be adjusted by the voltage
on GND-AB. However note also that this logarithmic part of the
response is not FPN corrected by the on-chip offset correction
circuitry.
The signal swing (and thus the dynamic range) is extended by
increasing the VDD_RESET (pins 59/79) to 5.5 V. This is
mode of operation is not further documented.
Table 2. shows the pins of the IC that are related to the image
sensor core, describing their functionality.
Table 2. Pins of the image sensor core
Digital controls
SYNC_YR\
5
Reset right Y shift register (low active, 0 = sync)
CLK_YR
6
Clock right Y shift register (shifts on falling edge)
EOS_YR\
7
(output) low 1st CLK_YR pulse after last row (low active)
SYNC_X\
28
Reset X shift register (low active, 0 = sync)
CLK_X
29
Clock X shift register (shifts on falling edge)
EOS_X\
8
(output) Low 1st CLK_X pulse after last active column (low active)
SYNC_YL\
36
Reset left Y shift register (low active, 0 = sync)
CLK_YL
37
Clock left Y shift register (shifts on falling edge)
EOS_YL\
38
Low 1st CLK_YL pulse after last row
SHY
30
Parallel Y track & hold (1 = hold, 0 = track) apply pulse pattern - see
sensor timing diagram
SIN
35
Column amplifier calibration pulse
1 = calibrate - see sensor timing diagram
SELECT
40
Selects row indicated by left/right shift register high active (1= select
row)
Apply 5 V DC for normal operation
RESET
41
Resets row indicated by left/right shift register high active (1 = reset)
Apply pulse pattern - see timing diagram
L/R\
80
Use left or right register for SELECT and RESET
1 = left / 0 = right - see sensor timing
SUBSMPL
84
Activate viewfinder mode (1:4 sub sampling = 320 x 256 pixels) high
active, 1 = sub sampling
Reference voltages
DCCON
31
Control voltage for the DCREF voltage generation Connect to ground
by default
DCREF
32
Reference voltage (output), to be decoupled to GND
Should be about 1.2V, can be adjusted by DCCON
NBIASARRAY
1
1 MegaOhm to VDD and decouple to ground by 100 nF capacitor
PBIAS2
2
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
PBIAS
3
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
XMUX_NBIAS
4
100K to VDD and decouple to ground by 100 nF capacitor
[+] Feedback
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYII4SM1300AA-QWC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:IBIS4-1300 1.3 MPxl Rolling Shutter CMOS Image Sensor |
| CYII4SM6600AB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:6.6 MP CMOS Image Sensor |
| CYII4SM6600AB-HDC | 制造商:Cypress Semiconductor 功能描述: |
| CYII4SM6600AB-QDC | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR B/W CMOS 2210X3002PIXELS 68PIN LCC - Boxed Product (Development Kits) 制造商:Cypress Semiconductor 功能描述:CYII4SM6600AB-QDC |
| CYII4SM6600AB-QWC | 功能描述:IC SENSOR IMAGE MONO 68-LCC RoHS:否 類別:傳感器，轉換器 >> 圖像，相機 系列:- 標準包裝:480 系列:- 象素大小:6.7µm x 6.7µm 有源象素陣列:768H x 488V 每秒幀數(shù):52 電源電壓:3.3V 類型:CMOS 成像 封裝/外殼:48-QFP 供應商設備封裝:48-QFP 包裝:托盤 請注意:* 配用:4H2105-ND - HEADBOARD FOR KAC-004014H2104-ND - KIT EVAL FOR KAC-00401 其它名稱:4H20954H2095-NDKAC-00401-CBC-LB-A0 |
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