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參數(shù)資料
| 型號(hào)： | CYK256K16MCBU-55BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Pseudo Static RAM |
| 中文描述： | 256K X 16 PSEUDO STATIC RAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 305K |
| 代理商： | CYK256K16MCBU-55BVXI |
CYK256K16MCCB
MoBL3
Document #: 38-05585 Rev. *F
Page 4 of 10
AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
V
Switching Characteristics
Over the Operating Range
[10]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK[14]
Write Cycle
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
Notes:
10.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0V to V
CC(typ.)
, and output loading of the specified I
/I
as shown in the “AC Test Loads and Waveforms” section.
11. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
12.The internal Write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
13.High-Z and Low-Z parameters are characterized and are not 100% tested.
14.To achieve 55-ns performance, the read access should be CE controlled. In this case t
is the critical parameter and t
is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
Description
55 ns
[14]
Min.
60 ns
70 ns
Unit
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[11, 13]
OE HIGH to High Z
[11, 13]
CE LOW to Low Z
[11, 13]
CE HIGH to High Z
[11, 13]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[11, 13]
BLE/BHE HIGH to HIGH Z
[11, 13]
Address Skew
55
60
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
60
70
5
8
10
55
25
60
25
70
35
5
5
5
25
25
25
2
2
5
25
55
25
60
25
70
5
5
5
10
0
10
5
25
10
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
55
45
45
0
0
40
60
45
45
0
0
40
70
60
55
0
0
45
ns
ns
ns
ns
ns
ns
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
TH
Equivalentto:
THé VENINEQUIVALENT
R
TH
ALL INPUT PULSES
R1
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|---|---|
| CYK256K16MCBU-70BVXI | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCB | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-55BVI | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-60BVI | 4-Mbit (256K x 16) Pseudo Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK256K16MCBU-70BVXI | 功能描述:IC PSRAM 4MBIT 70NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CYK256K16MCBU-70BVXIT | 功能描述:IC PSRAM 4MBIT 70NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CYK256K16MCCB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-60BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
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