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參數(shù)資料
| 型號： | CYK256K16SCCB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Pseudo Static RAM |
| 中文描述： | 4兆位（256K × 16）偽靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 307K |
| 代理商： | CYK256K16SCCB |
CYK256K16SCCB
Document #: 38-05526 Rev. *H
Page 4 of 10
AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
V
Switching Characteristics
(Over the Operating Range)
[10]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
Description
–55
–60
–70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[11, 12]
OE HIGH to High Z
[11, 12]
CE
1
LOW and CE
2
HIGH to
Low Z
[11, 12]
CE
1
HIGH and CE
2
LOW to
High Z
[11, 12]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[11, 12]
BLE/BHE HIGH to High-Z
[11, 12]
Address Skew
Write Cycle
[13]
t
WC
Write Cycle Time
t
SCE
CE
1
LOW and CE
2
HIGH to Write End
t
AW
Address Set-up to Write End
t
HA
Address Hold from Write End
t
SA
Address Set-up to Write Start
55
[14]
60
70
ns
ns
ns
ns
ns
ns
ns
ns
55
60
70
5
8
10
55
25
60
25
70
35
5
5
5
25
25
25
5
5
5
t
HZCE
25
25
25
ns
t
DBE
t
LZBE
t
HZBE
t
SK[14]
55
60
70
ns
ns
ns
ns
5
5
5
10
0
10
5
25
10
55
45
45
0
0
60
45
45
0
0
70
60
55
0
0
ns
ns
ns
ns
ns
Notes:
10.Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ),
and output loading of
the specified I
OL
/I
OH
and 30-pF load capacitance
11. t
, t
, t
and t
transitions are measured when the outputs enter a high-impedance state.
12.High-Z and Low-Z parameters are characterized and are not 100% tested.
13.The internal write time of the memory is defined by the overlap of WE, CE
= V
, CE
= V
, BHE and/or BLE =V
. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates write.
14.To achieve 55-ns performance, the read access should be CE controlled. In this case t
is the critical parameter and t
is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
Fall Time = 1 V/ns
OUTPUT
V
TH
ALL INPUT PULSES
R
TH
R1
[+] Feedback
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