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參數(shù)資料
| 型號： | CYK256K16SCCBU-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Pseudo Static RAM |
| 中文描述： | 256K X 16 PSEUDO STATIC RAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 307K |
| 代理商： | CYK256K16SCCBU-55BVI |
CYK256K16SCCB
Document #: 38-05526 Rev. *H
Page 5 of 10
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[11, 12]
WE HIGH to Low Z
[11, 12]
40
50
25
0
40
50
25
0
45
55
25
0
ns
ns
ns
ns
ns
ns
25
25
25
5
5
5
Switching Characteristics
(Over the Operating Range)
[10]
(continued)
Parameter
Description
–55
–60
–70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
[14, 15, 16]
Read Cycle 2 (OE Controlled)
[14, 16]
Notes:
15.Device is continuously selected. OE, CE = V
IL
.
16.WE is HIGH for Read Cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
tAA
tOHA
t
SK
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
HIGH
IMPEDANCE
OE
CE
1
I
CC
ADDRESS
CE
2
VCC
t
HZBE
BHE
/
BLE
t
LZBE
t
HZCE
DATA OUT
t
DBE
t
SK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK256K16SCCBU-55BVIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 4MBIT 256KX16 55NS 48VFBGA - Tape and Reel |
| CYK256K16SCCBU-60BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16SCCBU-70BAI | 制造商:Cypress Semiconductor 功能描述: |
| CYK256K16SCCBU-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK512K16SCAU-55BAXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8-Mbit (512K x 16) Pseudo Static RAM |
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